Documentation / devicetree / bindings / spi / qcom,spi-geni-qcom.yaml


Based on kernel version 6.10. Page generated on 2024-07-16 09:00 EST.

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/qcom,spi-geni-qcom.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)

maintainers:
  - Andy Gross <agross@kernel.org>
  - Bjorn Andersson <bjorn.andersson@linaro.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  The QUP v3 core is a GENI based AHB slave that provides a common data path
  (an output FIFO and an input FIFO) for serial peripheral interface (SPI)
  mini-core.
 
  SPI in master mode supports up to 50MHz, up to four chip selects,
  programmable data path from 4 bits to 32 bits and numerous protocol variants.
 
  SPI Controller nodes must be child of GENI based Qualcomm Universal
  Peripharal. Please refer GENI based QUP wrapper controller node bindings
  described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml.

allOf:
  - $ref: /schemas/spi/spi-controller.yaml#

properties:
  compatible:
    const: qcom,geni-spi

  clocks:
    maxItems: 1

  clock-names:
    const: se

  dmas:
    maxItems: 2

  dma-names:
    items:
      - const: tx
      - const: rx

  interconnects:
    minItems: 2
    maxItems: 3

  interconnect-names:
    minItems: 2
    items:
      - const: qup-core
      - const: qup-config
      - const: qup-memory

  interrupts:
    maxItems: 1

  operating-points-v2: true

  power-domains:
    maxItems: 1

  reg:
    maxItems: 1

required:
  - compatible
  - clocks
  - clock-names
  - interrupts
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
    #include <dt-bindings/interconnect/qcom,sc7180.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/qcom-rpmpd.h>
 
    spi@880000 {
        compatible = "qcom,geni-spi";
        reg = <0x00880000 0x4000>;
        clock-names = "se";
        clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
        pinctrl-names = "default";
        pinctrl-0 = <&qup_spi0_default>;
        interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
        #address-cells = <1>;
        #size-cells = <0>;
        power-domains = <&rpmhpd SC7180_CX>;
        operating-points-v2 = <&qup_opp_table>;
        interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
                        <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
        interconnect-names = "qup-core", "qup-config";
    };

  - |
    #include <dt-bindings/dma/qcom-gpi.h>
 
    spi@884000 {
        compatible = "qcom,geni-spi";
        reg = <0x00884000 0x4000>;
        clock-names = "se";
        clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
        dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
               <&gpi_dma0 1 1 QCOM_GPI_SPI>;
        dma-names = "tx", "rx";
        pinctrl-names = "default";
        pinctrl-0 = <&qup_spi1_default>;
        interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
        #address-cells = <1>;
        #size-cells = <0>;
    };