Based on kernel version 7.0. Page generated on 2026-04-23 09:49 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/spi/andestech,ae350-spi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Andes ATCSPI200 SPI controller maintainers: - CL Wang <cl634@andestech.com> properties: compatible: oneOf: - items: - enum: - andestech,qilai-spi - const: andestech,ae350-spi - const: andestech,ae350-spi reg: maxItems: 1 clocks: maxItems: 1 num-cs: description: Number of chip selects supported maxItems: 1 dmas: items: - description: Transmit FIFO DMA channel - description: Receive FIFO DMA channel dma-names: items: - const: tx - const: rx patternProperties: "@[0-9a-f]+$": type: object additionalProperties: true properties: spi-rx-bus-width: items: - enum: [1, 4] spi-tx-bus-width: items: - enum: [1, 4] allOf: - $ref: spi-controller.yaml# required: - compatible - reg - clocks - dmas - dma-names unevaluatedProperties: false examples: - | spi@f0b00000 { compatible = "andestech,ae350-spi"; reg = <0xf0b00000 0x100>; clocks = <&clk_spi>; dmas = <&dma0 0>, <&dma0 1>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-cpol; spi-cpha; }; }; |