Documentation / devicetree / bindings / spi / st,stm32-qspi.yaml


Based on kernel version 6.10. Page generated on 2024-07-16 09:00 EST.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/st,stm32-qspi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI)

maintainers:
  - Christophe Kerello <christophe.kerello@foss.st.com>
  - Patrice Chotard <patrice.chotard@foss.st.com>

allOf:
  - $ref: spi-controller.yaml#

properties:
  compatible:
    const: st,stm32f469-qspi

  reg:
    items:
      - description: registers
      - description: memory mapping

  reg-names:
    items:
      - const: qspi
      - const: qspi_mm

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1

  resets:
    maxItems: 1

  dmas:
    items:
      - description: tx DMA channel
      - description: rx DMA channel

  dma-names:
    items:
      - const: tx
      - const: rx

  access-controllers:
    minItems: 1
    maxItems: 2

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/stm32mp1-clks.h>
    #include <dt-bindings/reset/stm32mp1-resets.h>
    spi@58003000 {
      compatible = "st,stm32f469-qspi";
      reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
      reg-names = "qspi", "qspi_mm";
      interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
      dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
             <&mdma1 22 0x10 0x100008 0x0 0x0>;
      dma-names = "tx", "rx";
      clocks = <&rcc QSPI_K>;
      resets = <&rcc QSPI_R>;
 
      #address-cells = <1>;
      #size-cells = <0>;
 
      flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0>;
        spi-rx-bus-width = <4>;
        spi-max-frequency = <108000000>;
      };
    };

...