Based on kernel version 6.12.4
. Page generated on 2024-12-12 21:01 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/spi/adi,axi-spi-engine.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices AXI SPI Engine Controller description: | The AXI SPI Engine controller is part of the SPI Engine framework[1] and allows memory mapped access to the SPI Engine control bus. This allows it to be used as a general purpose software driven SPI controller as well as some optional advanced acceleration and offloading capabilities. [1] https://wiki.analog.com/resources/fpga/peripherals/spi_engine maintainers: - Michael Hennerich <Michael.Hennerich@analog.com> - Nuno Sá <nuno.sa@analog.com> allOf: - $ref: /schemas/spi/spi-controller.yaml# properties: compatible: const: adi,axi-spi-engine-1.00.a reg: maxItems: 1 interrupts: maxItems: 1 clocks: items: - description: The AXI interconnect clock. - description: The SPI controller clock. clock-names: items: - const: s_axi_aclk - const: spi_clk required: - compatible - reg - interrupts - clocks - clock-names unevaluatedProperties: false examples: - | spi@44a00000 { compatible = "adi,axi-spi-engine-1.00.a"; reg = <0x44a00000 0x1000>; interrupts = <0 56 4>; clocks = <&clkc 15>, <&clkc 15>; clock-names = "s_axi_aclk", "spi_clk"; #address-cells = <1>; #size-cells = <0>; /* SPI devices */ }; |