Based on kernel version 7.3. Page generated on 2026-10-19 13:17 EDT.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/spi/cavium,octeon-3010-spi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cavium, Inc. OCTEON SoC SPI master controller description: The Cavium OCTEON SPI controller is an SPI master controller found in OCTEON SoCs. maintainers: - Rob Herring <robh@kernel.org> allOf: - $ref: spi-controller.yaml# properties: compatible: const: cavium,octeon-3010-spi reg: maxItems: 1 interrupts: maxItems: 1 required: - compatible - reg - interrupts unevaluatedProperties: false examples: - | soc { #address-cells = <2>; #size-cells = <2>; spi@1070000001000 { compatible = "cavium,octeon-3010-spi"; reg = <0x10700 0x00001000 0x0 0x100>; interrupts = <0 58>; #address-cells = <1>; #size-cells = <0>; eeprom@0 { compatible = "st,m95256", "atmel,at25"; reg = <0>; spi-max-frequency = <5000000>; spi-cpha; spi-cpol; pagesize = <64>; size = <32768>; address-width = <16>; }; }; }; ... |