Based on kernel version 7.2. Page generated on 2026-08-20 08:41 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/phy/fsl,lynx-10g.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale Lynx 10G SerDes PHY maintainers: - Vladimir Oltean <vladimir.oltean@nxp.com> description: The 10G Lynx is a multi-protocol SerDes block which handles networking, PCIe, SATA and other high-speed interfaces. It is present on most QorIQ and Layerscape SoCs. The register map is common, but the integration is SoC-specific, with the differences consisting in register endianness, the number of lanes, protocol converters available per lane and their location in the PCCR registers. Some SoCs have multiple SerDes blocks and those differ in their protocol capabilities per lane. properties: compatible: enum: - fsl,ls1028a-serdes - fsl,ls1046a-serdes1 - fsl,ls1046a-serdes2 - fsl,ls1088a-serdes1 - fsl,ls1088a-serdes2 - fsl,ls2088a-serdes1 - fsl,ls2088a-serdes2 reg: maxItems: 1 big-endian: true "#phy-cells": const: 1 "#address-cells": const: 1 "#size-cells": const: 0 patternProperties: "^phy@[0-7]$": type: object description: SerDes lane (single RX/TX differential pair) properties: reg: minimum: 0 maximum: 7 description: Lane index as seen in register map "#phy-cells": const: 0 required: - reg - "#phy-cells" additionalProperties: false required: - compatible - reg - "#phy-cells" - "#address-cells" - "#size-cells" allOf: - if: properties: compatible: contains: enum: - fsl,ls1028a-serdes - fsl,ls1046a-serdes1 - fsl,ls1046a-serdes2 - fsl,ls1088a-serdes1 - fsl,ls1088a-serdes2 then: patternProperties: "^phy@[0-7]$": properties: reg: minimum: 0 maximum: 3 - if: properties: compatible: enum: - fsl,ls1046a-serdes1 - fsl,ls1046a-serdes2 then: required: - big-endian else: properties: big-endian: false additionalProperties: false examples: - | soc { #address-cells = <2>; #size-cells = <2>; serdes@1ea0000 { compatible = "fsl,ls1028a-serdes"; reg = <0x0 0x1ea0000 0x0 0xffff>; #address-cells = <1>; #size-cells = <0>; #phy-cells = <1>; phy@0 { reg = <0>; #phy-cells = <0>; }; phy@1 { reg = <1>; #phy-cells = <0>; }; phy@2 { reg = <2>; #phy-cells = <0>; }; phy@3 { reg = <3>; #phy-cells = <0>; }; }; }; |