Based on kernel version 7.0. Page generated on 2026-04-23 09:48 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/phy/spacemit,k1-pcie-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: SpacemiT K1 PCIe PHY maintainers: - Alex Elder <elder@riscstar.com> description: > Two PHYs on the SpacemiT K1 SoC used for only for PCIe. These PHYs must be configured using calibration values that are determined by a third "combo PHY". The combo PHY determines these calibration values during probe so they can be used for the two PCIe-only PHYs. The PHY uses an external oscillator as a reference clock. During normal operation, the PCIe host driver is responsible for ensuring all other clocks needed by a PHY are enabled, and all resets affecting the PHY are deasserted. properties: compatible: const: spacemit,k1-pcie-phy reg: items: - description: PHY control registers clocks: items: - description: External oscillator used by the PHY PLL clock-names: const: refclk resets: items: - description: PHY reset; remains deasserted after initialization reset-names: const: phy "#phy-cells": const: 0 required: - compatible - reg - clocks - clock-names - resets - reset-names - "#phy-cells" additionalProperties: false examples: - | #include <dt-bindings/clock/spacemit,k1-syscon.h> phy@c0c10000 { compatible = "spacemit,k1-pcie-phy"; reg = <0xc0c10000 0x1000>; clocks = <&vctcxo_24m>; clock-names = "refclk"; resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; reset-names = "phy"; #phy-cells = <0>; }; |