Based on kernel version 7.2. Page generated on 2026-08-20 08:41 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/phy/econet,en751221-pcie-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: EcoNet PCI-Express PHY for EcoNet EN751221 and EN7528 maintainers: - Caleb James DeLisle <cjd@cjdns.fr> description: The PCIe PHY supports physical layer functionality for PCIe Gen1 and Gen1/Gen2 ports. On these SoCs, port 0 is a Gen1-only port while port 1 is Gen1/Gen2 capable. properties: compatible: enum: - econet,en751221-pcie-gen1 - econet,en751221-pcie-gen2 - econet,en7528-pcie-gen1 - econet,en7528-pcie-gen2 reg: maxItems: 1 "#phy-cells": const: 0 required: - compatible - reg - "#phy-cells" additionalProperties: false examples: - | soc { #address-cells = <1>; #size-cells = <1>; pcie-phy@1faf2000 { compatible = "econet,en7528-pcie-gen1"; reg = <0x1faf2000 0x1000>; #phy-cells = <0>; }; }; ... |