Based on kernel version 6.10
. Page generated on 2024-07-16 09:00 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/phy/mediatek,mt7988-xfi-tphy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: MediaTek MT7988 XFI T-PHY maintainers: - Daniel Golle <daniel@makrotopia.org> description: The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in MediaTek's 10G-capabale MT7988 SoC. In MediaTek's SDK sources, this unit is referred to as "pextp". properties: compatible: const: mediatek,mt7988-xfi-tphy reg: maxItems: 1 clocks: items: - description: XFI PHY clock - description: XFI register clock clock-names: items: - const: xfipll - const: topxtal resets: items: - description: Reset controller corresponding to the phy instance. mediatek,usxgmii-performance-errata: $ref: /schemas/types.yaml#/definitions/flag description: One instance of the T-PHY on MT7988 suffers from a performance problem in 10GBase-R mode which needs a work-around in the driver. This flag enables a work-around ajusting an analog phy setting and is required for XFI Port0 of the MT7988 SoC to be in compliance with the SFP specification. "#phy-cells": const: 0 required: - compatible - reg - clocks - clock-names - resets - "#phy-cells" additionalProperties: false examples: - | #include <dt-bindings/clock/mediatek,mt7988-clk.h> soc { #address-cells = <2>; #size-cells = <2>; phy@11f20000 { compatible = "mediatek,mt7988-xfi-tphy"; reg = <0 0x11f20000 0 0x10000>; clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>; clock-names = "xfipll", "topxtal"; resets = <&watchdog 14>; mediatek,usxgmii-performance-errata; #phy-cells = <0>; }; }; ... |