Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm PCIe2 PHY controller maintainers: - Vinod Koul <vkoul@kernel.org> description: The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm platforms. properties: compatible: items: - const: qcom,qcs404-pcie2-phy - const: qcom,pcie2-phy reg: items: - description: PHY register set clocks: items: - description: a clock-specifier pair for the "pipe" clock clock-output-names: maxItems: 1 "#clock-cells": const: 0 "#phy-cells": const: 0 vdda-vp-supply: description: low voltage regulator vdda-vph-supply: description: high voltage regulator resets: maxItems: 2 reset-names: items: - const: phy - const: pipe required: - compatible - reg - clocks - clock-output-names - "#clock-cells" - "#phy-cells" - vdda-vp-supply - vdda-vph-supply - resets - reset-names additionalProperties: false examples: - | #include <dt-bindings/clock/qcom,gcc-qcs404.h> phy@7786000 { compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; reg = <0x07786000 0xb8>; clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, <&gcc GCC_PCIE_0_PIPE_ARES>; reset-names = "phy", "pipe"; vdda-vp-supply = <&vreg_l3_1p05>; vdda-vph-supply = <&vreg_l5_1p8>; clock-output-names = "pcie_0_pipe_clk"; #clock-cells = <0>; #phy-cells = <0>; }; ... |