Based on kernel version 6.15
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/phy/rockchip,rk3588-hdptx-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Rockchip SoC HDMI/eDP Transmitter Combo PHY maintainers: - Cristian Ciocaltea <cristian.ciocaltea@collabora.com> properties: compatible: oneOf: - enum: - rockchip,rk3588-hdptx-phy - items: - enum: - rockchip,rk3576-hdptx-phy - const: rockchip,rk3588-hdptx-phy reg: maxItems: 1 clocks: items: - description: Reference clock - description: APB clock clock-names: items: - const: ref - const: apb "#clock-cells": const: 0 "#phy-cells": const: 0 resets: minItems: 4 maxItems: 7 reset-names: minItems: 4 maxItems: 7 rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle description: Some PHY related data is accessed through GRF regs. required: - compatible - reg - clocks - clock-names - "#phy-cells" - resets - reset-names - rockchip,grf allOf: - if: properties: compatible: contains: enum: - rockchip,rk3576-hdptx-phy then: properties: resets: minItems: 4 maxItems: 4 reset-names: items: - const: apb - const: init - const: cmn - const: lane else: properties: resets: minItems: 7 maxItems: 7 reset-names: items: - const: phy - const: apb - const: init - const: cmn - const: lane - const: ropll - const: lcpll additionalProperties: false examples: - | #include <dt-bindings/clock/rockchip,rk3588-cru.h> #include <dt-bindings/reset/rockchip,rk3588-cru.h> soc { #address-cells = <2>; #size-cells = <2>; phy@fed60000 { compatible = "rockchip,rk3588-hdptx-phy"; reg = <0x0 0xfed60000 0x0 0x2000>; clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; clock-names = "ref", "apb"; #phy-cells = <0>; resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, <&cru SRST_HDPTX0_LCPLL>; reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll"; rockchip,grf = <&hdptxphy_grf>; }; }; |