Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 | # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- $id: http://devicetree.org/schemas/phy/allwinner,sun8i-h3-usb-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Allwinner H3 USB PHY maintainers: - Chen-Yu Tsai <wens@csie.org> - Maxime Ripard <mripard@kernel.org> properties: "#phy-cells": const: 1 compatible: enum: - allwinner,sun8i-h3-usb-phy - allwinner,sun50i-h616-usb-phy reg: items: - description: PHY Control registers - description: PHY PMU0 registers - description: PHY PMU1 registers - description: PHY PMU2 registers - description: PHY PMU3 registers reg-names: items: - const: phy_ctrl - const: pmu0 - const: pmu1 - const: pmu2 - const: pmu3 clocks: minItems: 4 items: - description: USB OTG PHY bus clock - description: USB Host 0 PHY bus clock - description: USB Host 1 PHY bus clock - description: USB Host 2 PHY bus clock - description: PMU clock for host port 2 clock-names: minItems: 4 items: - const: usb0_phy - const: usb1_phy - const: usb2_phy - const: usb3_phy - const: pmu2_clk resets: items: - description: USB OTG reset - description: USB Host 1 Controller reset - description: USB Host 2 Controller reset - description: USB Host 3 Controller reset reset-names: items: - const: usb0_reset - const: usb1_reset - const: usb2_reset - const: usb3_reset usb0_id_det-gpios: maxItems: 1 description: GPIO to the USB OTG ID pin usb0_vbus_det-gpios: maxItems: 1 description: GPIO to the USB OTG VBUS detect pin usb0_vbus_power-supply: description: Power supply to detect the USB OTG VBUS usb0_vbus-supply: description: Regulator controlling USB OTG VBUS usb1_vbus-supply: description: Regulator controlling USB1 Host controller usb2_vbus-supply: description: Regulator controlling USB2 Host controller usb3_vbus-supply: description: Regulator controlling USB3 Host controller required: - "#phy-cells" - compatible - clocks - clock-names - reg - reg-names - resets - reset-names allOf: - if: properties: compatible: contains: enum: - allwinner,sun50i-h616-usb-phy then: properties: clocks: minItems: 5 clock-names: minItems: 5 else: properties: clocks: maxItems: 4 clock-names: maxItems: 4 additionalProperties: false examples: - | #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/sun8i-h3-ccu.h> #include <dt-bindings/reset/sun8i-h3-ccu.h> phy@1c19400 { #phy-cells = <1>; compatible = "allwinner,sun8i-h3-usb-phy"; reg = <0x01c19400 0x2c>, <0x01c1a800 0x4>, <0x01c1b800 0x4>, <0x01c1c800 0x4>, <0x01c1d800 0x4>; reg-names = "phy_ctrl", "pmu0", "pmu1", "pmu2", "pmu3"; clocks = <&ccu CLK_USB_PHY0>, <&ccu CLK_USB_PHY1>, <&ccu CLK_USB_PHY2>, <&ccu CLK_USB_PHY3>; clock-names = "usb0_phy", "usb1_phy", "usb2_phy", "usb3_phy"; resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>, <&ccu RST_USB_PHY2>, <&ccu RST_USB_PHY3>; reset-names = "usb0_reset", "usb1_reset", "usb2_reset", "usb3_reset"; usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; usb3_vbus-supply = <®_usb3_vbus>; }; |