Based on kernel version 6.19. Page generated on 2026-02-12 08:38 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/phy/renesas,rzg3e-usb3-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Renesas RZ/G3E USB 3.0 PHY maintainers: - Biju Das <biju.das.jz@bp.renesas.com> properties: compatible: const: renesas,r9a09g047-usb3-phy reg: maxItems: 1 clocks: items: - description: APB bus clock - description: USB 2.0 PHY reference clock - description: USB 3.0 PHY reference clock clock-names: items: - const: pclk - const: core - const: ref_alt_clk_p power-domains: maxItems: 1 resets: maxItems: 1 '#phy-cells': const: 0 required: - compatible - reg - clocks - clock-names - power-domains - resets - '#phy-cells' additionalProperties: false examples: - | #include <dt-bindings/clock/renesas,r9a09g047-cpg.h> usb-phy@15870000 { compatible = "renesas,r9a09g047-usb3-phy"; reg = <0x15870000 0x10000>; clocks = <&cpg CPG_MOD 0xb0>, <&cpg CPG_CORE 13>, <&cpg CPG_CORE 12>; clock-names = "pclk", "core", "ref_alt_clk_p"; power-domains = <&cpg>; resets = <&cpg 0xaa>; #phy-cells = <0>; }; |