Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/phy/brcm,cygnus-pcie-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Broadcom Cygnus PCIe PHY maintainers: - Ray Jui <ray.jui@broadcom.com> - Scott Branden <scott.branden@broadcom.com> properties: $nodename: pattern: "^pcie[-|_]phy(@.*)?$" compatible: items: - const: brcm,cygnus-pcie-phy reg: maxItems: 1 description: > Base address and length of the PCIe PHY block "#address-cells": const: 1 "#size-cells": const: 0 patternProperties: "^pcie-phy@[0-9]+$": type: object additionalProperties: false description: > PCIe PHY child nodes properties: reg: maxItems: 1 description: > The PCIe PHY port number "#phy-cells": const: 0 required: - reg - "#phy-cells" required: - compatible - reg - "#address-cells" - "#size-cells" additionalProperties: false examples: - | pcie_phy: pcie_phy@301d0a0 { compatible = "brcm,cygnus-pcie-phy"; reg = <0x0301d0a0 0x14>; #address-cells = <1>; #size-cells = <0>; pcie0_phy: pcie-phy@0 { reg = <0>; #phy-cells = <0>; }; pcie1_phy: pcie-phy@1 { reg = <1>; #phy-cells = <0>; }; }; |