Based on kernel version 7.0. Page generated on 2026-04-23 09:48 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/interrupt-controller/renesas,r9a09g077-icu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Renesas RZ/{T2H,N2H} Interrupt Controller maintainers: - Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> allOf: - $ref: /schemas/interrupt-controller.yaml# description: The Interrupt Controller (ICU) handles software-triggered interrupts (INTCPU), external interrupts (IRQ and SEI), error interrupts and DMAC requests. properties: compatible: oneOf: - const: renesas,r9a09g077-icu # RZ/T2H - items: - enum: - renesas,r9a09g087-icu # RZ/N2H - const: renesas,r9a09g077-icu reg: items: - description: Non-safety registers (INTCPU0-13, IRQ0-13) - description: Safety registers (INTCPU14-15, IRQ14-15, SEI) '#interrupt-cells': description: The first cell is the SPI number of the interrupt, as per user manual. The second cell is used to specify the flag. const: 2 '#address-cells': const: 0 interrupt-controller: true interrupts: items: - description: Software interrupt 0 - description: Software interrupt 1 - description: Software interrupt 2 - description: Software interrupt 3 - description: Software interrupt 4 - description: Software interrupt 5 - description: Software interrupt 6 - description: Software interrupt 7 - description: Software interrupt 8 - description: Software interrupt 9 - description: Software interrupt 10 - description: Software interrupt 11 - description: Software interrupt 12 - description: Software interrupt 13 - description: Software interrupt 14 - description: Software interrupt 15 - description: External pin interrupt 0 - description: External pin interrupt 1 - description: External pin interrupt 2 - description: External pin interrupt 3 - description: External pin interrupt 4 - description: External pin interrupt 5 - description: External pin interrupt 6 - description: External pin interrupt 7 - description: External pin interrupt 8 - description: External pin interrupt 9 - description: External pin interrupt 10 - description: External pin interrupt 11 - description: External pin interrupt 12 - description: External pin interrupt 13 - description: External pin interrupt 14 - description: External pin interrupt 15 - description: System error interrupt - description: Cortex-A55 error event 0 - description: Cortex-A55 error event 1 - description: Cortex-R52 CPU 0 error event 0 - description: Cortex-R52 CPU 0 error event 1 - description: Cortex-R52 CPU 1 error event 0 - description: Cortex-R52 CPU 1 error event 1 - description: Peripherals error event 0 - description: Peripherals error event 1 - description: DSMIF error event 0 - description: DSMIF error event 1 - description: ENCIF error event 0 - description: ENCIF error event 1 interrupt-names: items: - const: intcpu0 - const: intcpu1 - const: intcpu2 - const: intcpu3 - const: intcpu4 - const: intcpu5 - const: intcpu6 - const: intcpu7 - const: intcpu8 - const: intcpu9 - const: intcpu10 - const: intcpu11 - const: intcpu12 - const: intcpu13 - const: intcpu14 - const: intcpu15 - const: irq0 - const: irq1 - const: irq2 - const: irq3 - const: irq4 - const: irq5 - const: irq6 - const: irq7 - const: irq8 - const: irq9 - const: irq10 - const: irq11 - const: irq12 - const: irq13 - const: irq14 - const: irq15 - const: sei - const: ca55-err0 - const: ca55-err1 - const: cr520-err0 - const: cr520-err1 - const: cr521-err0 - const: cr521-err1 - const: peri-err0 - const: peri-err1 - const: dsmif-err0 - const: dsmif-err1 - const: encif-err0 - const: encif-err1 clocks: maxItems: 1 power-domains: maxItems: 1 required: - compatible - reg - '#interrupt-cells' - '#address-cells' - interrupt-controller - interrupts - interrupt-names - clocks - power-domains unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h> icu: interrupt-controller@802a0000 { compatible = "renesas,r9a09g077-icu"; reg = <0x802a0000 0x10000>, <0x812a0000 0x50>; #interrupt-cells = <2>; #address-cells = <0>; interrupt-controller; interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 7 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 11 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 14 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 16 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 408 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 409 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 412 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 413 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 415 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 416 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 418 IRQ_TYPE_EDGE_RISING>; interrupt-names = "intcpu0", "intcpu1", "intcpu2", "intcpu3", "intcpu4", "intcpu5", "intcpu6", "intcpu7", "intcpu8", "intcpu9", "intcpu10", "intcpu11", "intcpu12", "intcpu13", "intcpu14", "intcpu15", "irq0", "irq1", "irq2", "irq3", "irq4", "irq5", "irq6", "irq7", "irq8", "irq9", "irq10", "irq11", "irq12", "irq13", "irq14", "irq15", "sei", "ca55-err0", "ca55-err1", "cr520-err0", "cr520-err1", "cr521-err0", "cr521-err1", "peri-err0", "peri-err1", "dsmif-err0", "dsmif-err1", "encif-err0", "encif-err1"; clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; power-domains = <&cpg>; }; |