Documentation / devicetree / bindings / interrupt-controller / loongson,liointc.yaml


Based on kernel version 6.11. Page generated on 2024-09-24 08:21 EST.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Loongson Local I/O Interrupt Controller

maintainers:
  - Jiaxun Yang <jiaxun.yang@flygoat.com>

description: |
  This interrupt controller is found in the Loongson-3 family of chips and
  Loongson-2K series chips, as the primary package interrupt controller which
  can route local I/O interrupt to interrupt lines of cores.
  Be aware of the following points.
  1.The Loongson-2K0500 is a single core CPU;
  2.The Loongson-2K0500/2K1000 has 64 device interrupt sources as inputs, so we
    need to define two nodes in dts{i} to describe the "0-31" and "32-61" interrupt
    sources respectively.

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    enum:
      - loongson,liointc-1.0
      - loongson,liointc-1.0a
      - loongson,liointc-2.0

  reg:
    minItems: 1
    maxItems: 3

  reg-names:
    items:
      - const: main
      - const: isr0
      - const: isr1
    minItems: 2

  interrupt-controller: true

  interrupts:
    description:
      Interrupt source of the CPU interrupts.
    minItems: 1
    maxItems: 4

  interrupt-names:
    description: List of names for the parent interrupts.
    items:
      pattern: int[0-3]
    minItems: 1
    maxItems: 4
 
  '#interrupt-cells':
    const: 2

  loongson,parent_int_map:
    description: |
      This property points how the children interrupts will be mapped into CPU
      interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
      and each bit in the cell refers to a child interrupt from 0 to 31.
      If a CPU interrupt line didn't connect with liointc, then keep its
      cell with zero.
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 4
    maxItems: 4

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - interrupt-controller
  - '#interrupt-cells'
  - loongson,parent_int_map
 

unevaluatedProperties: false

if:
  properties:
    compatible:
      contains:
        enum:
          - loongson,liointc-2.0

then:
  properties:
    reg:
      minItems: 2
      maxItems: 3

  required:
    - reg-names

else:
  properties:
    reg:
      maxItems: 1

examples:
  - |
    iointc: interrupt-controller@3ff01400 {
      compatible = "loongson,liointc-1.0";
      reg = <0x3ff01400 0x64>;
 
      interrupt-controller;
      #interrupt-cells = <2>;
 
      interrupt-parent = <&cpuintc>;
      interrupts = <2>, <3>;
      interrupt-names = "int0", "int1";
 
      loongson,parent_int_map = <0xf0ffffff>, /* int0 */
                                <0x0f000000>, /* int1 */
                                <0x00000000>, /* int2 */
                                <0x00000000>; /* int3 */
 
    };
 
...