Based on kernel version 6.11
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # Copyright (C) Sunplus Co., Ltd. 2021 %YAML 1.2 --- $id: http://devicetree.org/schemas/interrupt-controller/sunplus,sp7021-intc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Sunplus SP7021 SoC Interrupt Controller maintainers: - Qin Jian <qinjian@cqplus1.com> properties: compatible: items: - const: sunplus,sp7021-intc reg: maxItems: 2 description: Specifies base physical address(s) and size of the controller regs. The 1st region include type/polarity/priority/mask regs. The 2nd region include clear/masked_ext0/masked_ext1/group regs. interrupt-controller: true "#interrupt-cells": const: 2 description: The first cell is the IRQ number, the second cell is the trigger type as defined in interrupt.txt in this directory. interrupts: maxItems: 2 description: EXT_INT0 & EXT_INT1, 2 interrupts references to primary interrupt controller. required: - compatible - reg - interrupt-controller - "#interrupt-cells" - interrupts additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> intc: interrupt-controller@9c000780 { compatible = "sunplus,sp7021-intc"; reg = <0x9c000780 0x80>, <0x9c000a80 0x80>; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, /* EXT_INT0 */ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; /* EXT_INT1 */ }; ... |