Based on kernel version 6.11
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/interrupt-controller/starfive,jh8100-intc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: StarFive External Interrupt Controller description: StarFive SoC JH8100 contain a external interrupt controller. It can be used to handle high-level input interrupt signals. It also send the output interrupt signal to RISC-V PLIC. maintainers: - Changhuang Liang <changhuang.liang@starfivetech.com> properties: compatible: const: starfive,jh8100-intc reg: maxItems: 1 clocks: description: APB clock for the interrupt controller maxItems: 1 resets: description: APB reset for the interrupt controller maxItems: 1 interrupts: maxItems: 1 interrupt-controller: true "#interrupt-cells": const: 1 required: - compatible - reg - clocks - resets - interrupts - interrupt-controller - "#interrupt-cells" additionalProperties: false examples: - | interrupt-controller@12260000 { compatible = "starfive,jh8100-intc"; reg = <0x12260000 0x10000>; clocks = <&syscrg_ne 76>; resets = <&syscrg_ne 13>; interrupts = <45>; interrupt-controller; #interrupt-cells = <1>; }; |