# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Aspeed AST2700 Interrupt Controller

description:
  This interrupt controller hardware is second level interrupt controller that
  is hooked to a parent interrupt controller. It's useful to combine multiple
  interrupt sources into 1 interrupt to parent interrupt controller.

maintainers:
  - Kevin Chen <kevin_chen@aspeedtech.com>

properties:
  compatible:
    enum:
      - aspeed,ast2700-intc-ic

  reg:
    maxItems: 1

  interrupt-controller: true
 
  '#interrupt-cells':
    const: 2
    description:
      The first cell is the IRQ number, the second cell is the trigger
      type as defined in interrupt.txt in this directory.

  interrupts:
    maxItems: 6
    description: |
      Depend to which INTC0 or INTC1 used.
      INTC0 and INTC1 are two kinds of interrupt controller with enable and raw
      status registers for use.
      INTC0 is used to assert GIC if interrupt in INTC1 asserted.
      INTC1 is used to assert INTC0 if interrupt of modules asserted.
      +-----+   +-------+     +---------+---module0
      | GIC |---| INTC0 |--+--| INTC1_0 |---module2
      |     |   |       |  |  |         |---...
      +-----+   +-------+  |  +---------+---module31
                           |
                           |   +---------+---module0
                           +---| INTC1_1 |---module2
                           |   |         |---...
                           |   +---------+---module31
                          ...
                           |   +---------+---module0
                           +---| INTC1_5 |---module2
                               |         |---...
                               +---------+---module31
 

required:
  - compatible
  - reg
  - interrupt-controller
  - '#interrupt-cells'
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
 
    bus {
        #address-cells = <2>;
        #size-cells = <2>;
 
        interrupt-controller@12101b00 {
            compatible = "aspeed,ast2700-intc-ic";
            reg = <0 0x12101b00 0 0x10>;
            #interrupt-cells = <2>;
            interrupt-controller;
            interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
        };
    };