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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: RISC-V Incoming MSI Controller (IMSIC) maintainers: - Anup Patel <anup@brainfault.org> description: | The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V AIA specification can be found at https://github.com/riscv/riscv-aia. The IMSIC is a per-CPU (or per-HART) device with separate interrupt file for each privilege level (machine or supervisor). The configuration of a IMSIC interrupt file is done using AIA CSRs and it also has a 4KB MMIO space to receive MSIs from devices. Each IMSIC interrupt file supports a fixed number of interrupt identities (to distinguish MSIs from devices) which is same for given privilege level across CPUs (or HARTs). The device tree of a RISC-V platform will have one IMSIC device tree node for each privilege level (machine or supervisor) which collectively describe IMSIC interrupt files at that privilege level across CPUs (or HARTs). The arrangement of IMSIC interrupt files in MMIO space of a RISC-V platform follows a particular scheme defined by the RISC-V AIA specification. A IMSIC group is a set of IMSIC interrupt files co-located in MMIO space and we can have multiple IMSIC groups (i.e. clusters, sockets, chiplets, etc) in a RISC-V platform. The MSI target address of a IMSIC interrupt file at given privilege level (machine or supervisor) encodes group index, HART index, and guest index (shown below). XLEN-1 > (HART Index MSB) 12 0 | | | | ------------------------------------------------------------- |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 | ------------------------------------------------------------- allOf: - $ref: /schemas/interrupt-controller.yaml# - $ref: /schemas/interrupt-controller/msi-controller.yaml# properties: compatible: items: - enum: - qemu,imsics - const: riscv,imsics reg: minItems: 1 maxItems: 16384 description: Base address of each IMSIC group. interrupt-controller: true "#interrupt-cells": const: 0 msi-controller: true "#msi-cells": const: 0 interrupts-extended: minItems: 1 maxItems: 16384 description: This property represents the set of CPUs (or HARTs) for which given device tree node describes the IMSIC interrupt files. Each node pointed to should be a riscv,cpu-intc node, which has a CPU node (i.e. RISC-V HART) as parent. riscv,num-ids: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 63 maximum: 2047 description: Number of interrupt identities supported by IMSIC interrupt file. riscv,num-guest-ids: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 63 maximum: 2047 description: Number of interrupt identities are supported by IMSIC guest interrupt file. When not specified it is assumed to be same as specified by the riscv,num-ids property. riscv,guest-index-bits: minimum: 0 maximum: 7 default: 0 description: Number of guest index bits in the MSI target address. riscv,hart-index-bits: minimum: 0 maximum: 15 description: Number of HART index bits in the MSI target address. When not specified it is calculated based on the interrupts-extended property. riscv,group-index-bits: minimum: 0 maximum: 7 default: 0 description: Number of group index bits in the MSI target address. riscv,group-index-shift: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 55 default: 24 description: The least significant bit position of the group index bits in the MSI target address. required: - compatible - reg - interrupt-controller - msi-controller - "#msi-cells" - interrupts-extended - riscv,num-ids unevaluatedProperties: false examples: - | // Example 1 (Machine-level IMSIC files with just one group): interrupt-controller@24000000 { compatible = "qemu,imsics", "riscv,imsics"; interrupts-extended = <&cpu1_intc 11>, <&cpu2_intc 11>, <&cpu3_intc 11>, <&cpu4_intc 11>; reg = <0x28000000 0x4000>; interrupt-controller; #interrupt-cells = <0>; msi-controller; #msi-cells = <0>; riscv,num-ids = <127>; }; - | // Example 2 (Supervisor-level IMSIC files with two groups): interrupt-controller@28000000 { compatible = "qemu,imsics", "riscv,imsics"; interrupts-extended = <&cpu1_intc 9>, <&cpu2_intc 9>, <&cpu3_intc 9>, <&cpu4_intc 9>; reg = <0x28000000 0x2000>, /* Group0 IMSICs */ <0x29000000 0x2000>; /* Group1 IMSICs */ interrupt-controller; #interrupt-cells = <0>; msi-controller; #msi-cells = <0>; riscv,num-ids = <127>; riscv,group-index-bits = <1>; riscv,group-index-shift = <24>; }; ... |