Documentation / devicetree / bindings / media / qcom,milos-iris.yaml


Based on kernel version 7.3. Page generated on 2026-10-19 13:17 EDT.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/qcom,milos-iris.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Milos SoC Iris video encoder and decoder

maintainers:
  - Alexander Koskovich <akoskovich@pm.me>

description:
  The Iris video processing unit on Qualcomm Milos SoC is a video encode and
  decode accelerator.

properties:
  compatible:
    enum:
      - qcom,milos-iris

  clocks:
    maxItems: 3

  clock-names:
    items:
      - const: iface
      - const: core
      - const: vcodec0_core

  dma-coherent: true

  interconnects:
    maxItems: 2

  interconnect-names:
    items:
      - const: cpu-cfg
      - const: video-mem

  iommus:
    maxItems: 2

  operating-points-v2: true
  opp-table:
    type: object

  power-domains:
    maxItems: 4

  power-domain-names:
    items:
      - const: venus
      - const: vcodec0
      - const: cx
      - const: mx

  resets:
    maxItems: 2

  reset-names:
    items:
      - const: bus
      - const: core

required:
  - compatible
  - dma-coherent
  - interconnects
  - interconnect-names
  - iommus
  - power-domain-names
  - resets
  - reset-names

allOf:
  - $ref: qcom,venus-common.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/clock/qcom,milos-gcc.h>
    #include <dt-bindings/clock/qcom,milos-videocc.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interconnect/qcom,icc.h>
    #include <dt-bindings/interconnect/qcom,milos-rpmh.h>
    #include <dt-bindings/power/qcom-rpmpd.h>
    #include <dt-bindings/power/qcom,rpmhpd.h>
 
    video-codec@aa00000 {
        compatible = "qcom,milos-iris";
        reg = <0x0aa00000 0xf0000>;
 
        clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
                 <&videocc VIDEO_CC_MVS0C_CLK>,
                 <&videocc VIDEO_CC_MVS0_CLK>;
        clock-names = "iface",
                      "core",
                      "vcodec0_core";
 
        dma-coherent;
        iommus = <&apps_smmu 0x1960 0>,
                 <&apps_smmu 0x1967 0>;
 
        interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
                         &cnoc_cfg SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
                        <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
        interconnect-names = "cpu-cfg",
                             "video-mem";
 
        interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 
        operating-points-v2 = <&iris_opp_table>;
 
        memory-region = <&video_mem>;
 
        power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
                        <&videocc VIDEO_CC_MVS0_GDSC>,
                        <&rpmhpd RPMHPD_CX>,
                        <&rpmhpd RPMHPD_MX>;
        power-domain-names = "venus",
                             "vcodec0",
                             "cx",
                             "mx";
 
        resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
                 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
        reset-names = "bus",
                      "core";
 
        iris_opp_table: opp-table {
            compatible = "operating-points-v2";
 
            opp-240000000 {
                opp-hz = /bits/ 64 <240000000>;
                required-opps = <&rpmhpd_opp_low_svs>,
                                <&rpmhpd_opp_svs>;
            };
 
            opp-338000000 {
                opp-hz = /bits/ 64 <338000000>;
                required-opps = <&rpmhpd_opp_svs>,
                                <&rpmhpd_opp_svs>;
            };
 
            opp-366000000 {
                opp-hz = /bits/ 64 <366000000>;
                required-opps = <&rpmhpd_opp_svs_l1>,
                                <&rpmhpd_opp_svs>;
            };
 
            opp-444000000 {
                opp-hz = /bits/ 64 <444000000>;
                required-opps = <&rpmhpd_opp_nom>,
                                <&rpmhpd_opp_svs_l1>;
            };
 
            opp-552000000 {
                opp-hz = /bits/ 64 <552000000>;
                required-opps = <&rpmhpd_opp_turbo>,
                                <&rpmhpd_opp_nom>;
            };
        };
    };