Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/media/allwinner,sun8i-a83t-mipi-csi2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Allwinner A83T MIPI CSI-2 maintainers: - Paul Kocialkowski <paul.kocialkowski@bootlin.com> properties: compatible: const: allwinner,sun8i-a83t-mipi-csi2 reg: maxItems: 1 interrupts: maxItems: 1 clocks: items: - description: Bus Clock - description: Module Clock - description: MIPI-specific Clock - description: Misc CSI Clock clock-names: items: - const: bus - const: mod - const: mipi - const: misc resets: maxItems: 1 ports: $ref: /schemas/graph.yaml#/properties/ports properties: port@0: $ref: /schemas/graph.yaml#/$defs/port-base description: Input port, connect to a MIPI CSI-2 sensor properties: reg: const: 0 endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false properties: data-lanes: minItems: 1 maxItems: 4 required: - data-lanes unevaluatedProperties: false port@1: $ref: /schemas/graph.yaml#/properties/port description: Output port, connect to a CSI controller required: - port@0 - port@1 required: - compatible - reg - interrupts - clocks - clock-names - resets - ports additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/sun8i-a83t-ccu.h> #include <dt-bindings/reset/sun8i-a83t-ccu.h> mipi_csi2: csi@1cb1000 { compatible = "allwinner,sun8i-a83t-mipi-csi2"; reg = <0x01cb1000 0x1000>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_CSI>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_MIPI_CSI>, <&ccu CLK_CSI_MISC>; clock-names = "bus", "mod", "mipi", "misc"; resets = <&ccu RST_BUS_CSI>; ports { #address-cells = <1>; #size-cells = <0>; mipi_csi2_in: port@0 { reg = <0>; mipi_csi2_in_ov8865: endpoint { data-lanes = <1 2 3 4>; remote-endpoint = <&ov8865_out_mipi_csi2>; }; }; mipi_csi2_out: port@1 { reg = <1>; mipi_csi2_out_csi: endpoint { remote-endpoint = <&csi_in_mipi_csi2>; }; }; }; }; ... |