Based on kernel version 6.16. Page generated on 2025-08-06 08:57 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/media/qcom,x1e80100-camss.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm X1E80100 Camera Subsystem (CAMSS) maintainers: - Bryan O'Donoghue <bryan.odonoghue@linaro.org> description: The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. properties: compatible: const: qcom,x1e80100-camss reg: maxItems: 17 reg-names: items: - const: csid0 - const: csid1 - const: csid2 - const: csid_lite0 - const: csid_lite1 - const: csid_wrapper - const: csiphy0 - const: csiphy1 - const: csiphy2 - const: csiphy4 - const: csitpg0 - const: csitpg1 - const: csitpg2 - const: vfe0 - const: vfe1 - const: vfe_lite0 - const: vfe_lite1 clocks: maxItems: 29 clock-names: items: - const: camnoc_nrt_axi - const: camnoc_rt_axi - const: core_ahb - const: cpas_ahb - const: cpas_fast_ahb - const: cpas_vfe0 - const: cpas_vfe1 - const: cpas_vfe_lite - const: cphy_rx_clk_src - const: csid - const: csid_csiphy_rx - const: csiphy0 - const: csiphy0_timer - const: csiphy1 - const: csiphy1_timer - const: csiphy2 - const: csiphy2_timer - const: csiphy4 - const: csiphy4_timer - const: gcc_axi_hf - const: gcc_axi_sf - const: vfe0 - const: vfe0_fast_ahb - const: vfe1 - const: vfe1_fast_ahb - const: vfe_lite - const: vfe_lite_ahb - const: vfe_lite_cphy_rx - const: vfe_lite_csid interrupts: maxItems: 13 interrupt-names: items: - const: csid0 - const: csid1 - const: csid2 - const: csid_lite0 - const: csid_lite1 - const: csiphy0 - const: csiphy1 - const: csiphy2 - const: csiphy4 - const: vfe0 - const: vfe1 - const: vfe_lite0 - const: vfe_lite1 interconnects: maxItems: 4 interconnect-names: items: - const: ahb - const: hf_mnoc - const: sf_mnoc - const: sf_icp_mnoc iommus: maxItems: 8 power-domains: items: - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. power-domain-names: items: - const: ife0 - const: ife1 - const: top vdd-csiphy-0p8-supply: description: Phandle to a 0.8V regulator supply to a PHY. vdd-csiphy-1p2-supply: description: Phandle to 1.8V regulator supply to a PHY. ports: $ref: /schemas/graph.yaml#/properties/ports description: CSI input ports. patternProperties: "^port@[0-3]+$": $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false description: Input port for receiving CSI data from a CSIPHY. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false properties: clock-lanes: maxItems: 1 data-lanes: minItems: 1 maxItems: 4 required: - clock-lanes - data-lanes required: - compatible - reg - reg-names - clocks - clock-names - interrupts - interrupt-names - interconnects - interconnect-names - iommus - power-domains - power-domain-names - vdd-csiphy-0p8-supply - vdd-csiphy-1p2-supply - ports additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,x1e80100-gcc.h> #include <dt-bindings/clock/qcom,x1e80100-camcc.h> #include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> #include <dt-bindings/power/qcom-rpmpd.h> soc { #address-cells = <2>; #size-cells = <2>; camss: isp@acb6000 { compatible = "qcom,x1e80100-camss"; reg = <0 0x0acb7000 0 0x2000>, <0 0x0acb9000 0 0x2000>, <0 0x0acbb000 0 0x2000>, <0 0x0acc6000 0 0x1000>, <0 0x0acca000 0 0x1000>, <0 0x0acb6000 0 0x1000>, <0 0x0ace4000 0 0x1000>, <0 0x0ace6000 0 0x1000>, <0 0x0ace8000 0 0x1000>, <0 0x0acec000 0 0x4000>, <0 0x0acf6000 0 0x1000>, <0 0x0acf7000 0 0x1000>, <0 0x0acf8000 0 0x1000>, <0 0x0ac62000 0 0x4000>, <0 0x0ac71000 0 0x4000>, <0 0x0acc7000 0 0x2000>, <0 0x0accb000 0 0x2000>; reg-names = "csid0", "csid1", "csid2", "csid_lite0", "csid_lite1", "csid_wrapper", "csiphy0", "csiphy1", "csiphy2", "csiphy4", "csitpg0", "csitpg1", "csitpg2", "vfe0", "vfe1", "vfe_lite0", "vfe_lite1"; clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, <&camcc CAM_CC_CORE_AHB_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, <&camcc CAM_CC_CPAS_IFE_0_CLK>, <&camcc CAM_CC_CPAS_IFE_1_CLK>, <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, <&camcc CAM_CC_CPHY_RX_CLK_SRC>, <&camcc CAM_CC_CSID_CLK>, <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, <&camcc CAM_CC_CSIPHY0_CLK>, <&camcc CAM_CC_CSI0PHYTIMER_CLK>, <&camcc CAM_CC_CSIPHY1_CLK>, <&camcc CAM_CC_CSI1PHYTIMER_CLK>, <&camcc CAM_CC_CSIPHY2_CLK>, <&camcc CAM_CC_CSI2PHYTIMER_CLK>, <&camcc CAM_CC_CSIPHY4_CLK>, <&camcc CAM_CC_CSI4PHYTIMER_CLK>, <&gcc GCC_CAMERA_HF_AXI_CLK>, <&gcc GCC_CAMERA_SF_AXI_CLK>, <&camcc CAM_CC_IFE_0_CLK>, <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, <&camcc CAM_CC_IFE_1_CLK>, <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, <&camcc CAM_CC_IFE_LITE_CLK>, <&camcc CAM_CC_IFE_LITE_AHB_CLK>, <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, <&camcc CAM_CC_IFE_LITE_CSID_CLK>; clock-names = "camnoc_nrt_axi", "camnoc_rt_axi", "core_ahb", "cpas_ahb", "cpas_fast_ahb", "cpas_vfe0", "cpas_vfe1", "cpas_vfe_lite", "cphy_rx_clk_src", "csid", "csid_csiphy_rx", "csiphy0", "csiphy0_timer", "csiphy1", "csiphy1_timer", "csiphy2", "csiphy2_timer", "csiphy4", "csiphy4_timer", "gcc_axi_hf", "gcc_axi_sf", "vfe0", "vfe0_fast_ahb", "vfe1", "vfe1_fast_ahb", "vfe_lite", "vfe_lite_ahb", "vfe_lite_cphy_rx", "vfe_lite_csid"; interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; interrupt-names = "csid0", "csid1", "csid2", "csid_lite0", "csid_lite1", "csiphy0", "csiphy1", "csiphy2", "csiphy4", "vfe0", "vfe1", "vfe_lite0", "vfe_lite1"; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "ahb", "hf_mnoc", "sf_mnoc", "sf_icp_mnoc"; iommus = <&apps_smmu 0x800 0x60>, <&apps_smmu 0x860 0x60>, <&apps_smmu 0x1800 0x60>, <&apps_smmu 0x1860 0x60>, <&apps_smmu 0x18e0 0x00>, <&apps_smmu 0x1980 0x20>, <&apps_smmu 0x1900 0x00>, <&apps_smmu 0x19a0 0x20>; power-domains = <&camcc CAM_CC_IFE_0_GDSC>, <&camcc CAM_CC_IFE_1_GDSC>, <&camcc CAM_CC_TITAN_TOP_GDSC>; power-domain-names = "ife0", "ife1", "top"; vdd-csiphy-0p8-supply = <&csiphy_0p8_supply>; vdd-csiphy-1p2-supply = <&csiphy_1p2_supply>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; csiphy_ep0: endpoint { clock-lanes = <7>; data-lanes = <0 1>; remote-endpoint = <&sensor_ep>; }; }; }; }; }; |