Based on kernel version 6.10. Page generated on 2024-07-16 09:00 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/media/qcom,sc8280xp-camss.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm SC8280XP Camera Subsystem (CAMSS) maintainers: - Bryan O'Donoghue <bryan.odonoghue@linaro.org> description: | The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. properties: compatible: const: qcom,sc8280xp-camss clocks: maxItems: 40 clock-names: items: - const: camnoc_axi - const: cpas_ahb - const: csiphy0 - const: csiphy0_timer - const: csiphy1 - const: csiphy1_timer - const: csiphy2 - const: csiphy2_timer - const: csiphy3 - const: csiphy3_timer - const: vfe0_axi - const: vfe0 - const: vfe0_cphy_rx - const: vfe0_csid - const: vfe1_axi - const: vfe1 - const: vfe1_cphy_rx - const: vfe1_csid - const: vfe2_axi - const: vfe2 - const: vfe2_cphy_rx - const: vfe2_csid - const: vfe3_axi - const: vfe3 - const: vfe3_cphy_rx - const: vfe3_csid - const: vfe_lite0 - const: vfe_lite0_cphy_rx - const: vfe_lite0_csid - const: vfe_lite1 - const: vfe_lite1_cphy_rx - const: vfe_lite1_csid - const: vfe_lite2 - const: vfe_lite2_cphy_rx - const: vfe_lite2_csid - const: vfe_lite3 - const: vfe_lite3_cphy_rx - const: vfe_lite3_csid - const: gcc_axi_hf - const: gcc_axi_sf interrupts: maxItems: 20 interrupt-names: items: - const: csid1_lite - const: vfe_lite1 - const: csiphy3 - const: csid0 - const: vfe0 - const: csid1 - const: vfe1 - const: csid0_lite - const: vfe_lite0 - const: csiphy0 - const: csiphy1 - const: csiphy2 - const: csid2 - const: vfe2 - const: csid3_lite - const: csid2_lite - const: vfe_lite3 - const: vfe_lite2 - const: csid3 - const: vfe3 iommus: maxItems: 16 interconnects: maxItems: 4 interconnect-names: items: - const: cam_ahb - const: cam_hf_mnoc - const: cam_sf_mnoc - const: cam_sf_icp_mnoc power-domains: items: - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. - description: IFE3 GDSC - Image Front End, Global Distributed Switch Controller. - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. power-domain-names: items: - const: ife0 - const: ife1 - const: ife2 - const: ife3 - const: top ports: $ref: /schemas/graph.yaml#/properties/ports description: CSI input ports. properties: port@0: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false description: Input port for receiving CSI data from CSIPHY0. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false properties: clock-lanes: maxItems: 1 data-lanes: minItems: 1 maxItems: 4 required: - clock-lanes - data-lanes port@1: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false description: Input port for receiving CSI data from CSIPHY1. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false properties: clock-lanes: maxItems: 1 data-lanes: minItems: 1 maxItems: 4 required: - clock-lanes - data-lanes port@2: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false description: Input port for receiving CSI data from CSIPHY2. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false properties: clock-lanes: maxItems: 1 data-lanes: minItems: 1 maxItems: 4 required: - clock-lanes - data-lanes port@3: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false description: Input port for receiving CSI data from CSIPHY3. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false properties: clock-lanes: maxItems: 1 data-lanes: minItems: 1 maxItems: 4 required: - clock-lanes - data-lanes reg: maxItems: 20 reg-names: items: - const: csiphy2 - const: csiphy3 - const: csiphy0 - const: csiphy1 - const: vfe0 - const: csid0 - const: vfe1 - const: csid1 - const: vfe2 - const: csid2 - const: vfe_lite0 - const: csid0_lite - const: vfe_lite1 - const: csid1_lite - const: vfe_lite2 - const: csid2_lite - const: vfe_lite3 - const: csid3_lite - const: vfe3 - const: csid3 vdda-phy-supply: description: Phandle to a regulator supply to PHY core block. vdda-pll-supply: description: Phandle to 1.8V regulator supply to PHY refclk pll block. required: - clock-names - clocks - compatible - interconnects - interconnect-names - interrupts - interrupt-names - iommus - power-domains - power-domain-names - reg - reg-names - vdda-phy-supply - vdda-pll-supply additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> #include <dt-bindings/clock/qcom,sc8280xp-camcc.h> #include <dt-bindings/interconnect/qcom,sc8280xp.h> #include <dt-bindings/power/qcom-rpmpd.h> soc { #address-cells = <2>; #size-cells = <2>; camss: camss@ac5a000 { compatible = "qcom,sc8280xp-camss"; reg = <0 0x0ac5a000 0 0x2000>, <0 0x0ac5c000 0 0x2000>, <0 0x0ac65000 0 0x2000>, <0 0x0ac67000 0 0x2000>, <0 0x0acaf000 0 0x4000>, <0 0x0acb3000 0 0x1000>, <0 0x0acb6000 0 0x4000>, <0 0x0acba000 0 0x1000>, <0 0x0acbd000 0 0x4000>, <0 0x0acc1000 0 0x1000>, <0 0x0acc4000 0 0x4000>, <0 0x0acc8000 0 0x1000>, <0 0x0accb000 0 0x4000>, <0 0x0accf000 0 0x1000>, <0 0x0acd2000 0 0x4000>, <0 0x0acd6000 0 0x1000>, <0 0x0acd9000 0 0x4000>, <0 0x0acdd000 0 0x1000>, <0 0x0ace0000 0 0x4000>, <0 0x0ace4000 0 0x1000>; reg-names = "csiphy2", "csiphy3", "csiphy0", "csiphy1", "vfe0", "csid0", "vfe1", "csid1", "vfe2", "csid2", "vfe_lite0", "csid0_lite", "vfe_lite1", "csid1_lite", "vfe_lite2", "csid2_lite", "vfe_lite3", "csid3_lite", "vfe3", "csid3"; vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "csid1_lite", "vfe_lite1", "csiphy3", "csid0", "vfe0", "csid1", "vfe1", "csid0_lite", "vfe_lite0", "csiphy0", "csiphy1", "csiphy2", "csid2", "vfe2", "csid3_lite", "csid2_lite", "vfe_lite3", "vfe_lite2", "csid3", "vfe3"; power-domains = <&camcc IFE_0_GDSC>, <&camcc IFE_1_GDSC>, <&camcc IFE_2_GDSC>, <&camcc IFE_3_GDSC>, <&camcc TITAN_TOP_GDSC>; power-domain-names = "ife0", "ife1", "ife2", "ife3", "top"; clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, <&camcc CAMCC_CPAS_AHB_CLK>, <&camcc CAMCC_CSIPHY0_CLK>, <&camcc CAMCC_CSI0PHYTIMER_CLK>, <&camcc CAMCC_CSIPHY1_CLK>, <&camcc CAMCC_CSI1PHYTIMER_CLK>, <&camcc CAMCC_CSIPHY2_CLK>, <&camcc CAMCC_CSI2PHYTIMER_CLK>, <&camcc CAMCC_CSIPHY3_CLK>, <&camcc CAMCC_CSI3PHYTIMER_CLK>, <&camcc CAMCC_IFE_0_AXI_CLK>, <&camcc CAMCC_IFE_0_CLK>, <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, <&camcc CAMCC_IFE_0_CSID_CLK>, <&camcc CAMCC_IFE_1_AXI_CLK>, <&camcc CAMCC_IFE_1_CLK>, <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, <&camcc CAMCC_IFE_1_CSID_CLK>, <&camcc CAMCC_IFE_2_AXI_CLK>, <&camcc CAMCC_IFE_2_CLK>, <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, <&camcc CAMCC_IFE_2_CSID_CLK>, <&camcc CAMCC_IFE_3_AXI_CLK>, <&camcc CAMCC_IFE_3_CLK>, <&camcc CAMCC_IFE_3_CPHY_RX_CLK>, <&camcc CAMCC_IFE_3_CSID_CLK>, <&camcc CAMCC_IFE_LITE_0_CLK>, <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>, <&camcc CAMCC_IFE_LITE_0_CSID_CLK>, <&camcc CAMCC_IFE_LITE_1_CLK>, <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>, <&camcc CAMCC_IFE_LITE_1_CSID_CLK>, <&camcc CAMCC_IFE_LITE_2_CLK>, <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>, <&camcc CAMCC_IFE_LITE_2_CSID_CLK>, <&camcc CAMCC_IFE_LITE_3_CLK>, <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>, <&camcc CAMCC_IFE_LITE_3_CSID_CLK>, <&gcc GCC_CAMERA_HF_AXI_CLK>, <&gcc GCC_CAMERA_SF_AXI_CLK>; clock-names = "camnoc_axi", "cpas_ahb", "csiphy0", "csiphy0_timer", "csiphy1", "csiphy1_timer", "csiphy2", "csiphy2_timer", "csiphy3", "csiphy3_timer", "vfe0_axi", "vfe0", "vfe0_cphy_rx", "vfe0_csid", "vfe1_axi", "vfe1", "vfe1_cphy_rx", "vfe1_csid", "vfe2_axi", "vfe2", "vfe2_cphy_rx", "vfe2_csid", "vfe3_axi", "vfe3", "vfe3_cphy_rx", "vfe3_csid", "vfe_lite0", "vfe_lite0_cphy_rx", "vfe_lite0_csid", "vfe_lite1", "vfe_lite1_cphy_rx", "vfe_lite1_csid", "vfe_lite2", "vfe_lite2_cphy_rx", "vfe_lite2_csid", "vfe_lite3", "vfe_lite3_cphy_rx", "vfe_lite3_csid", "gcc_axi_hf", "gcc_axi_sf"; iommus = <&apps_smmu 0x2000 0x4e0>, <&apps_smmu 0x2020 0x4e0>, <&apps_smmu 0x2040 0x4e0>, <&apps_smmu 0x2060 0x4e0>, <&apps_smmu 0x2080 0x4e0>, <&apps_smmu 0x20e0 0x4e0>, <&apps_smmu 0x20c0 0x4e0>, <&apps_smmu 0x20a0 0x4e0>, <&apps_smmu 0x2400 0x4e0>, <&apps_smmu 0x2420 0x4e0>, <&apps_smmu 0x2440 0x4e0>, <&apps_smmu 0x2460 0x4e0>, <&apps_smmu 0x2480 0x4e0>, <&apps_smmu 0x24e0 0x4e0>, <&apps_smmu 0x24c0 0x4e0>, <&apps_smmu 0x24a0 0x4e0>; interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "cam_ahb", "cam_hf_mnoc", "cam_sf_mnoc", "cam_sf_icp_mnoc"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; csiphy_ep0: endpoint@0 { reg = <0>; clock-lanes = <7>; data-lanes = <0 1>; remote-endpoint = <&sensor_ep>; }; }; }; }; }; |