Based on kernel version 6.18. Page generated on 2025-12-02 09:03 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/media/mediatek,mt8173-vpu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mediatek MT8173 Video Processor Unit maintainers: - Ariel D'Alessandro <ariel.dalessandro@collabora.com> description: Video Processor Unit is a HW video controller. It controls HW Codec including H.264/VP8/VP9 Decode, H.264/VP8 Encode and Image Processor (scale/rotate/color convert). properties: compatible: const: mediatek,mt8173-vpu reg: maxItems: 2 reg-names: items: - const: tcm - const: cfg_reg interrupts: maxItems: 1 clocks: maxItems: 1 clock-names: items: - const: main memory-region: maxItems: 1 required: - compatible - reg - reg-names - interrupts - clocks - clock-names - memory-region additionalProperties: false examples: - | #include <dt-bindings/clock/mt8173-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> soc { #address-cells = <2>; #size-cells = <2>; vpu: vpu@10020000 { compatible = "mediatek,mt8173-vpu"; reg = <0 0x10020000 0 0x30000>, <0 0x10050000 0 0x100>; reg-names = "tcm", "cfg_reg"; interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; clocks = <&topckgen CLK_TOP_SCP_SEL>; clock-names = "main"; memory-region = <&vpu_dma_reserved>; }; }; ... |