# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/qcom,sm8750-iris.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SM8750 SoC Iris video encoder and decoder

maintainers:
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  The Iris video processing unit on Qualcomm SM8750 SoC is a video encode and
  decode accelerator.

properties:
  compatible:
    enum:
      - qcom,sm8750-iris

  clocks:
    maxItems: 6

  clock-names:
    items:
      - const: iface          # AXI0
      - const: core
      - const: vcodec0_core
      - const: iface1         # AXI1
      - const: core_freerun
      - const: vcodec0_core_freerun

  dma-coherent: true

  interconnects:
    maxItems: 2

  interconnect-names:
    items:
      - const: cpu-cfg
      - const: video-mem

  iommus:
    maxItems: 2

  operating-points-v2: true
  opp-table:
    type: object

  power-domains:
    maxItems: 4

  power-domain-names:
    items:
      - const: venus
      - const: vcodec0
      - const: mxc
      - const: mmcx

  resets:
    maxItems: 4

  reset-names:
    items:
      - const: bus0
      - const: bus1
      - const: core
      - const: vcodec0_core

required:
  - compatible
  - dma-coherent
  - interconnects
  - interconnect-names
  - iommus
  - power-domain-names
  - resets
  - reset-names

allOf:
  - $ref: qcom,venus-common.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/clock/qcom,sm8750-gcc.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interconnect/qcom,icc.h>
    #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
    #include <dt-bindings/power/qcom-rpmpd.h>
    #include <dt-bindings/power/qcom,rpmhpd.h>
 
    video-codec@aa00000 {
        compatible = "qcom,sm8750-iris";
        reg = <0x0aa00000 0xf0000>;
 
        clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
                 <&videocc_mvs0c_clk>,
                 <&videocc_mvs0_clk>,
                 <&gcc GCC_VIDEO_AXI1_CLK>,
                 <&videocc_mvs0c_freerun_clk>,
                 <&videocc_mvs0_freerun_clk>;
        clock-names = "iface",
                      "core",
                      "vcodec0_core",
                      "iface1",
                      "core_freerun",
                      "vcodec0_core_freerun";
 
        dma-coherent;
        iommus = <&apps_smmu 0x1940 0>,
                 <&apps_smmu 0x1947 0>;
 
        interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
                         &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
                        <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
        interconnect-names = "cpu-cfg",
                             "video-mem";
 
        interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 
        operating-points-v2 = <&iris_opp_table>;
 
        memory-region = <&video_mem>;
 
        power-domains = <&videocc_mvs0c_gdsc>,
                        <&videocc_mvs0_gdsc>,
                        <&rpmhpd RPMHPD_MXC>,
                        <&rpmhpd RPMHPD_MMCX>;
        power-domain-names = "venus",
                             "vcodec0",
                             "mxc",
                             "mmcx";
 
        resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
                 <&gcc GCC_VIDEO_AXI1_CLK_ARES>,
                 <&videocc_mvs0c_freerun_clk_ares>,
                 <&videocc_mvs0_freerun_clk_ares>;
        reset-names = "bus0",
                      "bus1",
                      "core",
                      "vcodec0_core";
 
        iris_opp_table: opp-table {
            compatible = "operating-points-v2";
 
            opp-240000000 {
                opp-hz = /bits/ 64 <240000000>;
                required-opps = <&rpmhpd_opp_low_svs_d1>,
                                <&rpmhpd_opp_low_svs_d1>;
            };
 
            opp-338000000 {
                opp-hz = /bits/ 64 <338000000>;
                required-opps = <&rpmhpd_opp_low_svs>,
                                <&rpmhpd_opp_low_svs>;
            };
 
            opp-420000000 {
                opp-hz = /bits/ 64 <420000000>;
                required-opps = <&rpmhpd_opp_svs>,
                                <&rpmhpd_opp_svs>;
            };
 
            opp-444000000 {
                opp-hz = /bits/ 64 <444000000>;
                required-opps = <&rpmhpd_opp_svs_l1>,
                                <&rpmhpd_opp_svs_l1>;
            };
 
            opp-533333334 {
                opp-hz = /bits/ 64 <533333334>;
                required-opps = <&rpmhpd_opp_nom>,
                                <&rpmhpd_opp_nom>;
            };
 
            opp-630000000 {
                opp-hz = /bits/ 64 <630000000>;
                required-opps = <&rpmhpd_opp_turbo>,
                                <&rpmhpd_opp_turbo>;
            };
        };
    };