Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Hantro G1/G2 VPU codecs implemented on i.MX8M SoCs maintainers: - Philipp Zabel <p.zabel@pengutronix.de> description: Hantro G1/G2 video decode accelerators present on i.MX8MQ SoCs. properties: compatible: oneOf: - const: nxp,imx8mq-vpu deprecated: true - const: nxp,imx8mq-vpu-g1 - const: nxp,imx8mq-vpu-g2 - const: nxp,imx8mm-vpu-g1 reg: maxItems: 1 interrupts: maxItems: 1 clocks: maxItems: 1 power-domains: maxItems: 1 required: - compatible - reg - interrupts - clocks additionalProperties: false examples: - | #include <dt-bindings/clock/imx8mq-clock.h> #include <dt-bindings/power/imx8mq-power.h> #include <dt-bindings/interrupt-controller/arm-gic.h> vpu_g1: video-codec@38300000 { compatible = "nxp,imx8mq-vpu-g1"; reg = <0x38300000 0x10000>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; }; - | #include <dt-bindings/clock/imx8mq-clock.h> #include <dt-bindings/power/imx8mq-power.h> #include <dt-bindings/interrupt-controller/arm-gic.h> vpu_g2: video-codec@38300000 { compatible = "nxp,imx8mq-vpu-g2"; reg = <0x38310000 0x10000>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; }; |