# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek Video Decode Accelerator

maintainers:
  - Yunfei Dong <yunfei.dong@mediatek.com>

description: |+
  Mediatek Video Decode is the video decode hardware present in Mediatek
  SoCs which supports high resolution decoding functionalities.

properties:
  compatible:
    enum:
      - mediatek,mt8173-vcodec-dec
      - mediatek,mt8183-vcodec-dec

  reg:
    minItems: 11
    maxItems: 11

  reg-names:
    items:
      - const: misc
      - const: ld
      - const: top
      - const: cm
      - const: ad
      - const: av
      - const: pp
      - const: hwd
      - const: hwq
      - const: hwb
      - const: hwg

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 8

  clock-names:
    minItems: 1
    maxItems: 8

  assigned-clocks: true

  assigned-clock-parents: true

  assigned-clock-rates: true

  power-domains:
    maxItems: 1

  iommus:
    minItems: 1
    maxItems: 32
    description: |
      List of the hardware port in respective IOMMU block for current Socs.
      Refer to bindings/iommu/mediatek,iommu.yaml.

  mediatek,vpu:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Describes point to vpu.

  mediatek,scp:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Describes point to scp.

  mediatek,vdecsys:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: Phandle to the vdecsys syscon node.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - iommus
  - mediatek,vdecsys

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt8183-vcodec-dec

    then:
      required:
        - mediatek,scp

      properties:
        clocks:
          minItems: 1
          maxItems: 1

        clock-names:
          items:
            - const: vdec

  - if:
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt8173-vcodec-dec

    then:
      required:
        - mediatek,vpu

      properties:
        clocks:
          minItems: 8
          maxItems: 8

        clock-names:
          items:
            - const: vcodecpll
            - const: univpll_d2
            - const: clk_cci400_sel
            - const: vdec_sel
            - const: vdecpll
            - const: vencpll
            - const: venc_lt_sel
            - const: vdec_bus_clk_src

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/memory/mt8173-larb-port.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/power/mt8173-power.h>
 
    vcodec_dec: vcodec@16020000 {
      compatible = "mediatek,mt8173-vcodec-dec";
      reg = <0x16020000 0x1000>,  /*VDEC_MISC*/
          <0x16021000 0x800>,   /*VDEC_LD*/
          <0x16021800 0x800>,   /*VDEC_TOP*/
          <0x16022000 0x1000>,  /*VDEC_CM*/
          <0x16023000 0x1000>,  /*VDEC_AD*/
          <0x16024000 0x1000>,  /*VDEC_AV*/
          <0x16025000 0x1000>,  /*VDEC_PP*/
          <0x16026800 0x800>,   /*VP8_VD*/
          <0x16027000 0x800>,   /*VP6_VD*/
          <0x16027800 0x800>,   /*VP8_VL*/
          <0x16028400 0x400>;   /*VP9_VD*/
      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
      iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
             <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
             <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
             <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
             <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
             <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
             <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
             <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
      mediatek,vpu = <&vpu>;
      mediatek,vdecsys = <&vdecsys>;
      power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
      clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
             <&topckgen CLK_TOP_UNIVPLL_D2>,
             <&topckgen CLK_TOP_CCI400_SEL>,
             <&topckgen CLK_TOP_VDEC_SEL>,
             <&topckgen CLK_TOP_VCODECPLL>,
             <&apmixedsys CLK_APMIXED_VENCPLL>,
             <&topckgen CLK_TOP_VENC_LT_SEL>,
             <&topckgen CLK_TOP_VCODECPLL_370P5>;
      clock-names = "vcodecpll",
                  "univpll_d2",
                  "clk_cci400_sel",
                  "vdec_sel",
                  "vdecpll",
                  "vencpll",
                  "venc_lt_sel",
                  "vdec_bus_clk_src";
      assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
                      <&topckgen CLK_TOP_CCI400_SEL>,
                      <&topckgen CLK_TOP_VDEC_SEL>,
                      <&apmixedsys CLK_APMIXED_VCODECPLL>,
                      <&apmixedsys CLK_APMIXED_VENCPLL>;
      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
                             <&topckgen CLK_TOP_UNIVPLL_D2>,
                             <&topckgen CLK_TOP_VCODECPLL>;
      assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
    };