# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/renesas,drif.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF)

maintainers:
  - Ramesh Shanmugasundaram <rashanmu@gmail.com>
  - Fabrizio Castro <fabrizio.castro.jz@renesas.com>

description: |
  R-Car Gen3 DRIF is a SPI like receive only slave device. A general
  representation of DRIF interfacing with a master device is shown below.
 
  +---------------------+                +---------------------+
  |                     |-----SCK------->|CLK                  |
  |       Master        |-----SS-------->|SYNC  DRIFn (slave)  |
  |                     |-----SD0------->|D0                   |
  |                     |-----SD1------->|D1                   |
  +---------------------+                +---------------------+
 
  As per datasheet, each DRIF channel (drifn) is made up of two internal
  channels (drifn0 & drifn1). These two internal channels share the common
  CLK & SYNC. Each internal channel has its own dedicated resources like
  irq, dma channels, address space & clock. This internal split is not
  visible to the external master device.
 
  The device tree model represents each internal channel as a separate node.
  The internal channels sharing the CLK & SYNC are tied together by their
  phandles using a property called "renesas,bonding". For the rest of
  the documentation, unless explicitly stated, the word channel implies an
  internal channel.
 
  When both internal channels are enabled they need to be managed together
  as one (i.e.) they cannot operate alone as independent devices. Out of the
  two, one of them needs to act as a primary device that accepts common
  properties of both the internal channels. This channel is identified by a
  property called "renesas,primary-bond".
 
  To summarize,
     * When both the internal channels that are bonded together are enabled,
       the zeroth channel is selected as primary-bond. This channels accepts
       properties common to all the members of the bond.
     * When only one of the bonded channels need to be enabled, the property
       "renesas,bonding" or "renesas,primary-bond" will have no effect. That
       enabled channel can act alone as any other independent device.

properties:
  compatible:
    items:
      - enum:
          - renesas,r8a7795-drif        # R-Car H3
          - renesas,r8a7796-drif        # R-Car M3-W
          - renesas,r8a77965-drif       # R-Car M3-N
          - renesas,r8a77990-drif       # R-Car E3
      - const: renesas,rcar-gen3-drif   # Generic R-Car Gen3 compatible device

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: fck

  resets:
    maxItems: 1

  dmas:
    minItems: 1
    maxItems: 2

  dma-names:
    minItems: 1
    items:
      - const: rx
      - const: rx

  renesas,bonding:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      The phandle to the other internal channel of DRIF

  power-domains:
    maxItems: 1

  renesas,primary-bond:
    type: boolean
    description:
      Indicates that the channel acts as primary among the bonded channels.

  port:
    $ref: /schemas/graph.yaml#/$defs/port-base
    unevaluatedProperties: false
    description:
      Child port node corresponding to the data input. The port node must
      contain at least one endpoint.

    properties:
      endpoint:
        $ref: /schemas/graph.yaml#/$defs/endpoint-base
        unevaluatedProperties: false

        properties:
          sync-active:
            $ref: /schemas/types.yaml#/definitions/uint32
            enum: [0, 1]
            description:
              Indicates sync signal polarity, 0/1 for low/high respectively.
              This property maps to SYNCAC bit in the hardware manual. The
              default is 1 (active high).

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - dmas
  - dma-names
  - renesas,bonding
  - power-domains

allOf:
  - if:
      required:
        - renesas,primary-bond
    then:
      required:
        - pinctrl-0
        - pinctrl-names
        - port

  - if:
      required:
        - port
    then:
      required:
        - pinctrl-0
        - pinctrl-names
    else:
      properties:
        pinctrl-0: false
        pinctrl-names: false

additionalProperties: false

examples:
  # Example with both internal channels enabled.
  #
  # When interfacing with a third party tuner device with two data pins as shown
  # below.
  #
  # +---------------------+                +---------------------+
  # |                     |-----SCK------->|CLK                  |
  # |       Master        |-----SS-------->|SYNC  DRIFn (slave)  |
  # |                     |-----SD0------->|D0                   |
  # |                     |-----SD1------->|D1                   |
  # +---------------------+                +---------------------+
  - |
    #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7795-sysc.h>
 
    soc {
            #address-cells = <2>;
            #size-cells = <2>;
 
            drif00: rif@e6f40000 {
                    compatible = "renesas,r8a7795-drif",
                                 "renesas,rcar-gen3-drif";
                    reg = <0 0xe6f40000 0 0x64>;
                    interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
                    clocks = <&cpg CPG_MOD 515>;
                    clock-names = "fck";
                    dmas = <&dmac1 0x20>, <&dmac2 0x20>;
                    dma-names = "rx", "rx";
                    power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                    renesas,bonding = <&drif01>;
                    resets = <&cpg 515>;
                    renesas,primary-bond;
                    pinctrl-0 = <&drif0_pins>;
                    pinctrl-names = "default";
                    port {
                            drif0_ep: endpoint {
                                 remote-endpoint = <&tuner_ep>;
                            };
                    };
            };
 
            drif01: rif@e6f50000 {
                    compatible = "renesas,r8a7795-drif",
                                 "renesas,rcar-gen3-drif";
                    reg = <0 0xe6f50000 0 0x64>;
                    interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
                    clocks = <&cpg CPG_MOD 514>;
                    clock-names = "fck";
                    dmas = <&dmac1 0x22>, <&dmac2 0x22>;
                    dma-names = "rx", "rx";
                    power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                    renesas,bonding = <&drif00>;
                    resets = <&cpg 514>;
            };
    };
 
  # Example with internal channel 1 alone enabled.
  #
  # When interfacing with a third party tuner device with one data pin as shown
  # below.
  #
  # +---------------------+                +---------------------+
  # |                     |-----SCK------->|CLK                  |
  # |       Master        |-----SS-------->|SYNC  DRIFn (slave)  |
  # |                     |                |D0 (unused)          |
  # |                     |-----SD-------->|D1                   |
  # +---------------------+                +---------------------+
  - |
    #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7795-sysc.h>
 
    soc {
            #address-cells = <2>;
            #size-cells = <2>;
 
            drif10: rif@e6f60000 {
                    compatible = "renesas,r8a7795-drif",
                                 "renesas,rcar-gen3-drif";
                    reg = <0 0xe6f60000 0 0x64>;
                    interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                    clocks = <&cpg CPG_MOD 513>;
                    clock-names = "fck";
                    dmas = <&dmac1 0x24>, <&dmac2 0x24>;
                    dma-names = "rx", "rx";
                    power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                    resets = <&cpg 513>;
                    renesas,bonding = <&drif11>;
            };
 
            drif11: rif@e6f70000 {
                    compatible = "renesas,r8a7795-drif",
                                 "renesas,rcar-gen3-drif";
                    reg = <0 0xe6f70000 0 0x64>;
                    interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                    clocks = <&cpg CPG_MOD 512>;
                    clock-names = "fck";
                    dmas = <&dmac1 0x26>, <&dmac2 0x26>;
                    dma-names = "rx", "rx";
                    power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                    resets = <&cpg 512>;
                    renesas,bonding = <&drif10>;
                    pinctrl-0 = <&drif1_pins>;
                    pinctrl-names = "default";
                    port {
                            drif1_ep: endpoint {
                                 remote-endpoint = <&tuner_ep1>;
                                 sync-active = <0>;
                            };
                    };
            };
    };
...