Based on kernel version 6.15
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/media/st,stm32-dcmipp.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 DCMIPP Digital Camera Memory Interface Pixel Processor maintainers: - Hugues Fruchet <hugues.fruchet@foss.st.com> - Alain Volmat <alain.volmat@foss.st.com> properties: compatible: enum: - st,stm32mp13-dcmipp - st,stm32mp25-dcmipp reg: maxItems: 1 interrupts: maxItems: 1 clocks: items: - description: bus clock - description: csi clock minItems: 1 clock-names: items: - const: kclk - const: mclk minItems: 1 resets: maxItems: 1 access-controllers: minItems: 1 maxItems: 2 port: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false description: DCMIPP supports a single port node with parallel bus. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false properties: bus-type: enum: [4, 5, 6] default: 5 bus-width: enum: [8, 10, 12, 14] default: 8 pclk-sample: true hsync-active: true vsync-active: true required: - compatible - reg - interrupts - clocks - resets - port allOf: - if: properties: compatible: contains: enum: - st,stm32mp13-dcmipp then: properties: clocks: maxItems: 1 clock-names: maxItems: 1 port: properties: endpoint: properties: bus-type: enum: [5, 6] else: properties: clocks: minItems: 2 clock-names: minItems: 2 additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/stm32mp13-clks.h> #include <dt-bindings/reset/stm32mp13-resets.h> dcmipp@5a000000 { compatible = "st,stm32mp13-dcmipp"; reg = <0x5a000000 0x400>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; resets = <&rcc DCMIPP_R>; clocks = <&rcc DCMIPP_K>; port { endpoint { remote-endpoint = <&mipid02_2>; bus-width = <8>; hsync-active = <0>; vsync-active = <0>; pclk-sample = <0>; }; }; }; ... |