Documentation / devicetree / bindings / gpio / fsl,mpc8323-qe-pario-bank.yaml


Based on kernel version 7.3. Page generated on 2026-10-19 13:17 EDT.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/fsl,mpc8323-qe-pario-bank.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale QUICC Engine Parallel I/O (QE PARIO) GPIO Bank

maintainers:
  - Christophe Leroy <christophe.leroy@csgroup.eu>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - fsl,mpc8360-qe-pario-bank
              - fsl,mpc8569-qe-pario-bank
          - const: fsl,mpc8323-qe-pario-bank
      - const: fsl,mpc8323-qe-pario-bank

  reg:
    maxItems: 1

  gpio-controller: true
 
  "#gpio-cells":
    const: 2
 
  "#address-cells":
    const: 0
 
  "#interrupt-cells":
    const: 2

  interrupt-map:
    description: |
      Specifies the mapping of GPIO lines to the parent interrupt controller, as the
      GPIO controller does not do interrupt handling itself.

required:
  - compatible
  - reg
  - gpio-controller
  - "#gpio-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
 
    gpio-controller@1400 {
        compatible = "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-pario-bank";
        reg = <0x1400 0x18>;
        gpio-controller;
        #gpio-cells = <2>;
    };
 
    gpio-controller@1418 {
        compatible = "fsl,mpc8323-qe-pario-bank";
        reg = <0x1418 0x18>;
        gpio-controller;
        #gpio-cells = <2>;
        #address-cells = <0>;
        #interrupt-cells = <2>;
        interrupt-map = <
          7 IRQ_TYPE_EDGE_FALLING  &pic 4 IRQ_TYPE_EDGE_FALLING
          7 IRQ_TYPE_EDGE_BOTH     &pic 4 IRQ_TYPE_EDGE_BOTH
          7 0                      &pic 4 IRQ_TYPE_NONE
 
          9 IRQ_TYPE_EDGE_FALLING  &pic 5 IRQ_TYPE_EDGE_FALLING
          9 IRQ_TYPE_EDGE_BOTH     &pic 5 IRQ_TYPE_EDGE_BOTH
          9 0                      &pic 5 IRQ_TYPE_NONE
 
          25 IRQ_TYPE_EDGE_FALLING &pic 6 IRQ_TYPE_EDGE_FALLING
          25 IRQ_TYPE_EDGE_BOTH    &pic 6 IRQ_TYPE_EDGE_BOTH
          25 0                     &pic 6 IRQ_TYPE_NONE
 
          27 IRQ_TYPE_EDGE_FALLING &pic 7 IRQ_TYPE_EDGE_FALLING
          27 IRQ_TYPE_EDGE_BOTH    &pic 7 IRQ_TYPE_EDGE_BOTH
          27 0                     &pic 7 IRQ_TYPE_NONE
        >;
    };