Based on kernel version 6.15
. Page generated on 2025-05-29 09:08 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/gpio/fairchild,74hc595.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Generic 8-bit shift register description: | NOTE: These chips nominally don't have a chip select pin. They do however have a rising-edge triggered latch clock (or storage register clock) pin, which behaves like an active-low chip select. After the bits are shifted into the shift register, CS# is driven high, which the 74HC595 sees as a rising edge on the latch clock that results in a transfer of the bits from the shift register to the storage register and thus to the output pins. _ _ _ _ shift clock ____| |_| |_..._| |_| |_________ latch clock * trigger ___ ________ chip select# |___________________| maintainers: - Maxime Ripard <mripard@kernel.org> properties: compatible: enum: - fairchild,74hc595 - nxp,74lvc594 reg: maxItems: 1 gpio-controller: true '#gpio-cells': description: The second cell is only used to specify the GPIO polarity. const: 2 registers-number: $ref: /schemas/types.yaml#/definitions/uint32 description: Number of daisy-chained shift registers enable-gpios: description: GPIO connected to the OE (Output Enable) pin. maxItems: 1 patternProperties: "^(hog-[0-9]+|.+-hog(-[0-9]+)?)$": type: object required: - gpio-hog required: - compatible - reg - gpio-controller - '#gpio-cells' - registers-number allOf: - $ref: /schemas/spi/spi-peripheral-props.yaml# unevaluatedProperties: false examples: - | spi { #address-cells = <1>; #size-cells = <0>; gpio5: gpio5@0 { compatible = "fairchild,74hc595"; reg = <0>; gpio-controller; #gpio-cells = <2>; registers-number = <4>; spi-max-frequency = <100000>; }; }; |