Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/gpio/fsl,qoriq-gpio.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale MPC512x/MPC8xxx/QorIQ/Layerscape GPIO controller maintainers: - Frank Li <Frank.Li@nxp.com> properties: compatible: oneOf: - enum: - fsl,mpc5121-gpio - fsl,mpc5125-gpio - fsl,mpc8349-gpio - fsl,mpc8572-gpio - fsl,mpc8610-gpio - fsl,pq3-gpio - items: - enum: - fsl,ls1021a-gpio - fsl,ls1028a-gpio - fsl,ls1043a-gpio - fsl,ls1046a-gpio - fsl,ls1088a-gpio - fsl,ls2080a-gpio - const: fsl,qoriq-gpio reg: maxItems: 1 interrupts: maxItems: 1 "#gpio-cells": const: 2 gpio-controller: true interrupt-controller: true "#interrupt-cells": const: 2 gpio-line-names: minItems: 1 maxItems: 32 little-endian: $ref: /schemas/types.yaml#/definitions/flag description: GPIO registers are used as little endian. If not present registers are used as big endian by default. required: - compatible - reg - interrupts - "#gpio-cells" additionalProperties: false examples: - | gpio@1100 { compatible = "fsl,mpc5125-gpio"; reg = <0x1100 0x080>; interrupts = <78 0x8>; gpio-controller; #gpio-cells = <2>; }; - | #include <dt-bindings/interrupt-controller/arm-gic.h> gpio@2300000 { compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; reg = <0x2300000 0x10000>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; little-endian; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; |