Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/gpio/brcm,xgs-iproc-gpio.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Broadcom XGS iProc GPIO controller maintainers: - Chris Packham <chris.packham@alliedtelesis.co.nz> description: | This controller is the Chip Common A GPIO present on a number of Broadcom switch ASICs with integrated SoCs. properties: compatible: const: brcm,iproc-gpio-cca reg: items: - description: the I/O address containing the GPIO controller registers. - description: the I/O address containing the Chip Common A interrupt registers. gpio-controller: true '#gpio-cells': const: 2 ngpios: minimum: 0 maximum: 32 interrupt-controller: true '#interrupt-cells': const: 2 interrupts: maxItems: 1 required: - compatible - reg - "#gpio-cells" - gpio-controller additionalProperties: false dependencies: interrupt-controller: [ interrupts ] examples: - | #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> gpio@18000060 { compatible = "brcm,iproc-gpio-cca"; #gpio-cells = <2>; reg = <0x18000060 0x50>, <0x18000000 0x50>; ngpios = <12>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; }; ... |