Based on kernel version 6.17
. Page generated on 2025-10-03 10:04 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/cavium,octeon-3860-gpio.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cavium Octeon 3860 GPIO controller maintainers: - Bartosz Golaszewski <brgl@bgdev.pl> properties: compatible: const: cavium,octeon-3860-gpio reg: maxItems: 1 gpio-controller: true '#gpio-cells': const: 2 interrupt-controller: true '#interrupt-cells': const: 2 interrupts: maxItems: 16 required: - compatible - reg - gpio-controller - '#gpio-cells' - interrupt-controller - '#interrupt-cells' - interrupts additionalProperties: false examples: - | bus { #address-cells = <2>; #size-cells = <2>; gpio@1070000000800 { compatible = "cavium,octeon-3860-gpio"; reg = <0x10700 0x00000800 0x0 0x100>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; /* The GPIO pin connect to 16 consecutive CUI bits */ interrupts = <0 16>, <0 17>, <0 18>, <0 19>, <0 20>, <0 21>, <0 22>, <0 23>, <0 24>, <0 25>, <0 26>, <0 27>, <0 28>, <0 29>, <0 30>, <0 31>; }; }; |