Documentation / devicetree / bindings / net / microchip,pic64hpsc-mdio.yaml


Based on kernel version 7.2. Page generated on 2026-08-20 08:41 EST.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/microchip,pic64hpsc-mdio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip PIC64-HPSC/HX MDIO controller

maintainers:
  - Charles Perry <charles.perry@microchip.com>

description:
  This is the MDIO bus controller present in Microchip PIC64-HPSC/HX SoCs. It
  supports C22 and C45 register access and is named "MDIO Initiator" in the
  documentation.

allOf:
  - $ref: mdio.yaml#

properties:
  compatible:
    oneOf:
      - const: microchip,pic64hpsc-mdio
      - items:
          - const: microchip,pic64hx-mdio
          - const: microchip,pic64hpsc-mdio

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-frequency:
    default: 2500000

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    bus {
        #address-cells = <2>;
        #size-cells = <2>;
 
        mdio@4000c21e000 {
            compatible = "microchip,pic64hpsc-mdio";
            reg = <0x400 0x0c21e000 0x0 0x1000>;
            #address-cells = <1>;
            #size-cells = <0>;
            clocks = <&svc_clk>;
            interrupt-parent = <&saplic0>;
            interrupts = <168 IRQ_TYPE_LEVEL_HIGH>;
 
            ethernet-phy@0 {
                reg = <0>;
            };
        };
    };