Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 | # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- $id: http://devicetree.org/schemas/net/smsc,lan91c111.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Smart Mixed-Signal Connectivity (SMSC) LAN91C9x/91C1xx Controller maintainers: - Nicolas Pitre <nico@fluxnic.net> allOf: - $ref: ethernet-controller.yaml# properties: compatible: const: smsc,lan91c111 reg: maxItems: 1 interrupts: maxItems: 1 reg-shift: true reg-io-width: enum: [ 1, 2, 4 ] default: 4 reset-gpios: description: GPIO connected to control RESET pin maxItems: 1 power-gpios: description: GPIO connect to control PWRDWN pin maxItems: 1 pxa-u16-align4: description: put in place the workaround the force all u16 writes to be 32 bits aligned type: boolean required: - compatible - reg - interrupts unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> ethernet@4010000 { compatible = "smsc,lan91c111"; reg = <0x40100000 0x10000>; phy-mode = "mii"; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <2>; }; |