Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/net/renesas,rzn1-gmac.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Renesas GMAC maintainers: - Romain Gantois <romain.gantois@bootlin.com> select: properties: compatible: contains: enum: - renesas,r9a06g032-gmac - renesas,rzn1-gmac required: - compatible allOf: - $ref: snps,dwmac.yaml# properties: compatible: items: - enum: - renesas,r9a06g032-gmac - const: renesas,rzn1-gmac - const: snps,dwmac pcs-handle: description: phandle pointing to a PCS sub-node compatible with renesas,rzn1-miic.yaml# required: - compatible unevaluatedProperties: false examples: - | #include <dt-bindings/clock/r9a06g032-sysctrl.h> #include <dt-bindings/interrupt-controller/arm-gic.h> ethernet@44000000 { compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; reg = <0x44000000 0x2000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; clock-names = "stmmaceth"; clocks = <&sysctrl R9A06G032_HCLK_GMAC0>; power-domains = <&sysctrl>; snps,multicast-filter-bins = <256>; snps,perfect-filter-entries = <128>; tx-fifo-depth = <2048>; rx-fifo-depth = <4096>; pcs-handle = <&mii_conv1>; phy-mode = "mii"; }; ... |