Based on kernel version 6.18. Page generated on 2025-12-02 09:03 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 | # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/net/qcom,ipq9574-ppe.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm IPQ packet process engine (PPE) maintainers: - Luo Jie <quic_luoj@quicinc.com> - Lei Wei <quic_leiwei@quicinc.com> - Suruchi Agarwal <quic_suruchia@quicinc.com> - Pavithra R <quic_pavir@quicinc.com> description: | The Ethernet functionality in the PPE (Packet Process Engine) is comprised of three components, the switch core, port wrapper and Ethernet DMA. The Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and two FIFO interfaces. One of the two FIFO interfaces is used for Ethernet port to host CPU communication using Ethernet DMA. The other is used communicating to the EIP engine which is used for IPsec offload. On the IPQ9574, the PPE includes 6 GMAC/XGMACs that can be connected with external Ethernet PHY. Switch core also includes BM (Buffer Management), QM (Queue Management) and SCH (Scheduler) modules for supporting the packet processing. The port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS) supporting various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There are 3 UNIPHY (PCS) instances supported on the IPQ9574. Ethernet DMA is used to transmit and receive packets between the six Ethernet ports and ARM host CPU. The follow diagram shows the PPE hardware block along with its connectivity to the external hardware blocks such clock hardware blocks (CMNPLL, GCC, NSS clock controller) and Ethernet PCS/PHY blocks. For depicting the PHY connectivity, one 4x1 Gbps PHY (QCA8075) and two 10 GBps PHYs are used as an example. +---------+ | 48 MHZ | +----+----+ |(clock) v +----+----+ +------| CMN PLL | | +----+----+ | |(clock) | v | +----+----+ +----+----+ (clock) +----+----+ | +---| NSSCC | | GCC |--------->| MDIO | | | +----+----+ +----+----+ +----+----+ | | |(clock & reset) |(clock) | | v v | | +----+---------------------+--+----------+----------+---------+ | | | +-----+ |EDMA FIFO | | EIP FIFO| | | | | SCH | +----------+ +---------+ | | | +-----+ | | | | | | +------+ +------+ +-------------------+ | | | | | BM | | QM | IPQ9574-PPE | L2/L3 Process | | | | | +------+ +------+ +-------------------+ | | | | | | | | | +-------+ +-------+ +-------+ +-------+ +-------+ +-------+ | | | | | MAC0 | | MAC1 | | MAC2 | | MAC3 | | XGMAC4| |XGMAC5 | | | | | +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ | | | | | | | | | | | | | +-----+---------+---------+---------+---------+---------+-----+ | | | | | | | | | | +---+---------+---------+---------+---+ +---+---+ +---+---+ +--+---->| PCS0 | | PCS1 | | PCS2 | |(clock) +---+---------+---------+---------+---+ +---+---+ +---+---+ | | | | | | | | +---+---------+---------+---------+---+ +---+---+ +---+---+ +------->| QCA8075 PHY | | PHY4 | | PHY5 | (clock) +-------------------------------------+ +-------+ +-------+ properties: compatible: enum: - qcom,ipq9574-ppe reg: maxItems: 1 clocks: items: - description: PPE core clock - description: PPE APB (Advanced Peripheral Bus) clock - description: PPE IPE (Ingress Process Engine) clock - description: PPE BM, QM and scheduler clock clock-names: items: - const: ppe - const: apb - const: ipe - const: btq resets: maxItems: 1 description: PPE reset, which is necessary before configuring PPE hardware interrupts: maxItems: 1 description: PPE switch miscellaneous interrupt interconnects: items: - description: Bus interconnect path leading to PPE switch core function - description: Bus interconnect path leading to PPE register access - description: Bus interconnect path leading to QoS generation - description: Bus interconnect path leading to timeout reference - description: Bus interconnect path leading to NSS NOC from memory NOC - description: Bus interconnect path leading to memory NOC from NSS NOC - description: Bus interconnect path leading to enhanced memory NOC from NSS NOC interconnect-names: items: - const: ppe - const: ppe_cfg - const: qos_gen - const: timeout_ref - const: nssnoc_memnoc - const: memnoc_nssnoc - const: memnoc_nssnoc_1 ethernet-dma: type: object additionalProperties: false description: EDMA (Ethernet DMA) is used to transmit packets between PPE and ARM host CPU. There are 32 TX descriptor rings, 32 TX completion rings, 24 RX descriptor rings and 8 RX fill rings supported. properties: clocks: items: - description: EDMA system clock - description: EDMA APB (Advanced Peripheral Bus) clock clock-names: items: - const: sys - const: apb resets: maxItems: 1 description: EDMA reset interrupts: minItems: 65 maxItems: 65 interrupt-names: minItems: 65 maxItems: 65 items: oneOf: - pattern: '^txcmpl_([1-2]?[0-9]|3[01])$' - pattern: '^rxfill_[0-7]$' - pattern: '^rxdesc_(1?[0-9]|2[0-3])$' - const: misc description: Interrupts "txcmpl_[0-31]" are the Ethernet DMA TX completion ring interrupts. Interrupts "rxfill_[0-7]" are the Ethernet DMA RX fill ring interrupts. Interrupts "rxdesc_[0-23]" are the Ethernet DMA RX Descriptor ring interrupts. Interrupt "misc" is the Ethernet DMA miscellaneous error interrupt. required: - clocks - clock-names - resets - interrupts - interrupt-names ethernet-ports: patternProperties: "^ethernet-port@[1-6]+$": type: object unevaluatedProperties: false $ref: ethernet-switch-port.yaml# properties: reg: minimum: 1 maximum: 6 description: PPE Ethernet port ID clocks: items: - description: Port MAC clock - description: Port RX clock - description: Port TX clock clock-names: items: - const: mac - const: rx - const: tx resets: items: - description: Port MAC reset - description: Port RX reset - description: Port TX reset reset-names: items: - const: mac - const: rx - const: tx required: - reg - clocks - clock-names - resets - reset-names required: - compatible - reg - clocks - clock-names - resets - interconnects - interconnect-names - ethernet-dma allOf: - $ref: ethernet-switch.yaml unevaluatedProperties: false examples: - | #include <dt-bindings/clock/qcom,ipq9574-gcc.h> #include <dt-bindings/clock/qcom,ipq9574-nsscc.h> #include <dt-bindings/interconnect/qcom,ipq9574.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/reset/qcom,ipq9574-nsscc.h> ethernet-switch@3a000000 { compatible = "qcom,ipq9574-ppe"; reg = <0x3a000000 0xbef800>; clocks = <&nsscc NSS_CC_PPE_SWITCH_CLK>, <&nsscc NSS_CC_PPE_SWITCH_CFG_CLK>, <&nsscc NSS_CC_PPE_SWITCH_IPE_CLK>, <&nsscc NSS_CC_PPE_SWITCH_BTQ_CLK>; clock-names = "ppe", "apb", "ipe", "btq"; resets = <&nsscc PPE_FULL_RESET>; interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>; interconnects = <&nsscc MASTER_NSSNOC_PPE &nsscc SLAVE_NSSNOC_PPE>, <&nsscc MASTER_NSSNOC_PPE_CFG &nsscc SLAVE_NSSNOC_PPE_CFG>, <&gcc MASTER_NSSNOC_QOSGEN_REF &gcc SLAVE_NSSNOC_QOSGEN_REF>, <&gcc MASTER_NSSNOC_TIMEOUT_REF &gcc SLAVE_NSSNOC_TIMEOUT_REF>, <&gcc MASTER_MEM_NOC_NSSNOC &gcc SLAVE_MEM_NOC_NSSNOC>, <&gcc MASTER_NSSNOC_MEMNOC &gcc SLAVE_NSSNOC_MEMNOC>, <&gcc MASTER_NSSNOC_MEM_NOC_1 &gcc SLAVE_NSSNOC_MEM_NOC_1>; interconnect-names = "ppe", "ppe_cfg", "qos_gen", "timeout_ref", "nssnoc_memnoc", "memnoc_nssnoc", "memnoc_nssnoc_1"; ethernet-dma { clocks = <&nsscc NSS_CC_PPE_EDMA_CLK>, <&nsscc NSS_CC_PPE_EDMA_CFG_CLK>; clock-names = "sys", "apb"; resets = <&nsscc EDMA_HW_RESET>; interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "txcmpl_0", "txcmpl_1", "txcmpl_2", "txcmpl_3", "txcmpl_4", "txcmpl_5", "txcmpl_6", "txcmpl_7", "txcmpl_8", "txcmpl_9", "txcmpl_10", "txcmpl_11", "txcmpl_12", "txcmpl_13", "txcmpl_14", "txcmpl_15", "txcmpl_16", "txcmpl_17", "txcmpl_18", "txcmpl_19", "txcmpl_20", "txcmpl_21", "txcmpl_22", "txcmpl_23", "txcmpl_24", "txcmpl_25", "txcmpl_26", "txcmpl_27", "txcmpl_28", "txcmpl_29", "txcmpl_30", "txcmpl_31", "rxfill_0", "rxfill_1", "rxfill_2", "rxfill_3", "rxfill_4", "rxfill_5", "rxfill_6", "rxfill_7", "rxdesc_0", "rxdesc_1", "rxdesc_2", "rxdesc_3", "rxdesc_4", "rxdesc_5", "rxdesc_6", "rxdesc_7", "rxdesc_8", "rxdesc_9", "rxdesc_10", "rxdesc_11", "rxdesc_12", "rxdesc_13", "rxdesc_14", "rxdesc_15", "rxdesc_16", "rxdesc_17", "rxdesc_18", "rxdesc_19", "rxdesc_20", "rxdesc_21", "rxdesc_22", "rxdesc_23", "misc"; }; ethernet-ports { #address-cells = <1>; #size-cells = <0>; ethernet-port@1 { reg = <1>; phy-mode = "qsgmii"; managed = "in-band-status"; phy-handle = <&phy0>; pcs-handle = <&pcs0_ch0>; clocks = <&nsscc NSS_CC_PORT1_MAC_CLK>, <&nsscc NSS_CC_PORT1_RX_CLK>, <&nsscc NSS_CC_PORT1_TX_CLK>; clock-names = "mac", "rx", "tx"; resets = <&nsscc PORT1_MAC_ARES>, <&nsscc PORT1_RX_ARES>, <&nsscc PORT1_TX_ARES>; reset-names = "mac", "rx", "tx"; }; ethernet-port@2 { reg = <2>; phy-mode = "qsgmii"; managed = "in-band-status"; phy-handle = <&phy1>; pcs-handle = <&pcs0_ch1>; clocks = <&nsscc NSS_CC_PORT2_MAC_CLK>, <&nsscc NSS_CC_PORT2_RX_CLK>, <&nsscc NSS_CC_PORT2_TX_CLK>; clock-names = "mac", "rx", "tx"; resets = <&nsscc PORT2_MAC_ARES>, <&nsscc PORT2_RX_ARES>, <&nsscc PORT2_TX_ARES>; reset-names = "mac", "rx", "tx"; }; ethernet-port@3 { reg = <3>; phy-mode = "qsgmii"; managed = "in-band-status"; phy-handle = <&phy2>; pcs-handle = <&pcs0_ch2>; clocks = <&nsscc NSS_CC_PORT3_MAC_CLK>, <&nsscc NSS_CC_PORT3_RX_CLK>, <&nsscc NSS_CC_PORT3_TX_CLK>; clock-names = "mac", "rx", "tx"; resets = <&nsscc PORT3_MAC_ARES>, <&nsscc PORT3_RX_ARES>, <&nsscc PORT3_TX_ARES>; reset-names = "mac", "rx", "tx"; }; ethernet-port@4 { reg = <4>; phy-mode = "qsgmii"; managed = "in-band-status"; phy-handle = <&phy3>; pcs-handle = <&pcs0_ch3>; clocks = <&nsscc NSS_CC_PORT4_MAC_CLK>, <&nsscc NSS_CC_PORT4_RX_CLK>, <&nsscc NSS_CC_PORT4_TX_CLK>; clock-names = "mac", "rx", "tx"; resets = <&nsscc PORT4_MAC_ARES>, <&nsscc PORT4_RX_ARES>, <&nsscc PORT4_TX_ARES>; reset-names = "mac", "rx", "tx"; }; ethernet-port@5 { reg = <5>; phy-mode = "usxgmii"; managed = "in-band-status"; phy-handle = <&phy4>; pcs-handle = <&pcs1_ch0>; clocks = <&nsscc NSS_CC_PORT5_MAC_CLK>, <&nsscc NSS_CC_PORT5_RX_CLK>, <&nsscc NSS_CC_PORT5_TX_CLK>; clock-names = "mac", "rx", "tx"; resets = <&nsscc PORT5_MAC_ARES>, <&nsscc PORT5_RX_ARES>, <&nsscc PORT5_TX_ARES>; reset-names = "mac", "rx", "tx"; }; ethernet-port@6 { reg = <6>; phy-mode = "usxgmii"; managed = "in-band-status"; phy-handle = <&phy5>; pcs-handle = <&pcs2_ch0>; clocks = <&nsscc NSS_CC_PORT6_MAC_CLK>, <&nsscc NSS_CC_PORT6_RX_CLK>, <&nsscc NSS_CC_PORT6_TX_CLK>; clock-names = "mac", "rx", "tx"; resets = <&nsscc PORT6_MAC_ARES>, <&nsscc PORT6_RX_ARES>, <&nsscc PORT6_TX_ARES>; reset-names = "mac", "rx", "tx"; }; }; }; |