Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/net/loongson,ls1b-gmac.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Loongson-1B Gigabit Ethernet MAC Controller maintainers: - Keguang Zhang <keguang.zhang@gmail.com> description: | Loongson-1B Gigabit Ethernet MAC Controller is based on Synopsys DesignWare MAC (version 3.50a). Main features - Dual 10/100/1000Mbps GMAC controllers - Full-duplex operation (IEEE 802.3x flow control automatic transmission) - Half-duplex operation (CSMA/CD Protocol and back-pressure support) - RX Checksum Offload - TX Checksum insertion - MII interface - RGMII interface select: properties: compatible: contains: enum: - loongson,ls1b-gmac required: - compatible properties: compatible: items: - enum: - loongson,ls1b-gmac - const: snps,dwmac-3.50a reg: maxItems: 1 clocks: maxItems: 1 clock-names: items: - const: stmmaceth interrupts: maxItems: 1 interrupt-names: items: - const: macirq loongson,ls1-syscon: $ref: /schemas/types.yaml#/definitions/phandle description: Phandle to the syscon containing some extra configurations including PHY interface mode. phy-mode: enum: - mii - rgmii-id required: - compatible - reg - clocks - clock-names - interrupts - interrupt-names - loongson,ls1-syscon allOf: - $ref: snps,dwmac.yaml# unevaluatedProperties: false examples: - | #include <dt-bindings/clock/loongson,ls1x-clk.h> #include <dt-bindings/interrupt-controller/irq.h> gmac0: ethernet@1fe10000 { compatible = "loongson,ls1b-gmac", "snps,dwmac-3.50a"; reg = <0x1fe10000 0x10000>; clocks = <&clkc LS1X_CLKID_AHB>; clock-names = "stmmaceth"; interrupt-parent = <&intc1>; interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; loongson,ls1-syscon = <&syscon>; phy-handle = <&phy0>; phy-mode = "mii"; snps,pbl = <1>; mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; phy0: ethernet-phy@0 { reg = <0x0>; }; }; }; |