Based on kernel version 7.2. Page generated on 2026-08-20 08:41 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/usb/cdns,usb3.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cadence USBSS and USBSSP DRD controller maintainers: - Pawel Laszczak <pawell@cadence.com> description: Cadence USB dual-role controller. Covers USBSS (SuperSpeed, USB 3.0) and USBSSP (SuperSpeed Plus, USB 3.1 gen2x1). Both variants share the same DRD/OTG register interface, so the driver auto-detects the controller version at runtime. properties: compatible: oneOf: - const: cdns,usb3 - items: - {} - const: cdns,cdnsp reg: minItems: 2 maxItems: 3 reg-names: minItems: 2 maxItems: 3 items: enum: [ otg, xhci, dev ] interrupts: minItems: 2 items: - description: XHCI host controller interrupt - description: Device controller interrupt - description: OTG/DRD controller interrupt - description: interrupt used to wake up core, e.g when usbcmd.rs is cleared by xhci core, this interrupt is optional interrupt-names: minItems: 2 items: - const: host - const: peripheral - const: otg - const: wakeup port: $ref: /schemas/graph.yaml#/properties/port description: This port is used with the 'usb-role-switch' property to connect the cdns3 to type C connector. maximum-speed: enum: [super-speed-plus, super-speed, high-speed, full-speed] phys: minItems: 1 maxItems: 2 phy-names: minItems: 1 maxItems: 2 items: anyOf: - const: cdns3,usb2-phy - const: cdns3,usb3-phy cdns,on-chip-buff-size: description: size of memory intended as internal memory for endpoints buffers expressed in KB $ref: /schemas/types.yaml#/definitions/uint16 cdns,phyrst-a-enable: description: Enable resetting of PHY if Rx fail is detected type: boolean dependencies: port: [ usb-role-switch ] required: - compatible - reg - reg-names - interrupts - interrupt-names allOf: - $ref: usb-drd.yaml# - $ref: usb-xhci.yaml# - if: properties: compatible: contains: const: cdns,cdnsp then: properties: reg: items: - description: XHCI Host controller registers - description: DEVICE controller registers reg-names: items: - const: xhci - const: dev interrupts: maxItems: 2 interrupt-names: items: - const: host - const: peripheral dr_mode: enum: [host, peripheral] else: properties: reg: items: - description: OTG controller registers - description: XHCI Host controller registers - description: DEVICE controller registers reg-names: items: - const: otg - const: xhci - const: dev interrupts: minItems: 3 maxItems: 4 interrupt-names: minItems: 3 unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> bus { #address-cells = <2>; #size-cells = <2>; usb@6000000 { compatible = "cdns,usb3"; reg = <0x00 0x6000000 0x00 0x10000>, <0x00 0x6010000 0x00 0x10000>, <0x00 0x6020000 0x00 0x10000>; reg-names = "otg", "xhci", "dev"; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "host", "peripheral", "otg"; maximum-speed = "super-speed"; dr_mode = "otg"; }; }; |