Based on kernel version 6.11
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 | # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- $id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Rockchip SuperSpeed DWC3 USB SoC controller maintainers: - Heiko Stuebner <heiko@sntech.de> description: The common content of the node is defined in snps,dwc3.yaml. Phy documentation is provided in the following places. USB2.0 PHY Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml Type-C PHY Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt select: properties: compatible: contains: enum: - rockchip,rk3328-dwc3 - rockchip,rk3568-dwc3 - rockchip,rk3588-dwc3 required: - compatible properties: compatible: items: - enum: - rockchip,rk3328-dwc3 - rockchip,rk3568-dwc3 - rockchip,rk3588-dwc3 - const: snps,dwc3 reg: maxItems: 1 interrupts: maxItems: 1 clocks: minItems: 3 items: - description: Controller reference clock, must to be 24 MHz - description: Controller suspend clock, must to be 24 MHz or 32 KHz - description: Master/Core clock, must to be >= 62.5 MHz for SS operation and >= 30MHz for HS operation - description: Controller grf clock OR UTMI clock - description: PIPE clock clock-names: minItems: 3 items: - const: ref_clk - const: suspend_clk - const: bus_clk - enum: - grf_clk - utmi - const: pipe power-domains: maxItems: 1 resets: maxItems: 1 reset-names: const: usb3-otg unevaluatedProperties: false required: - compatible - reg - interrupts - clocks - clock-names allOf: - $ref: snps,dwc3.yaml# - if: properties: compatible: contains: const: rockchip,rk3328-dwc3 then: properties: clocks: minItems: 3 maxItems: 4 clock-names: minItems: 3 items: - const: ref_clk - const: suspend_clk - const: bus_clk - const: grf_clk - if: properties: compatible: contains: const: rockchip,rk3568-dwc3 then: properties: clocks: maxItems: 3 clock-names: maxItems: 3 - if: properties: compatible: contains: const: rockchip,rk3588-dwc3 then: properties: clock-names: minItems: 3 items: - const: ref_clk - const: suspend_clk - const: bus_clk - const: utmi - const: pipe examples: - | #include <dt-bindings/clock/rk3328-cru.h> #include <dt-bindings/interrupt-controller/arm-gic.h> bus { #address-cells = <2>; #size-cells = <2>; usbdrd3_0: usb@fe800000 { compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; reg = <0x0 0xfe800000 0x0 0x100000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, <&cru ACLK_USB3OTG>; clock-names = "ref_clk", "suspend_clk", "bus_clk", "grf_clk"; dr_mode = "otg"; }; }; |