Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/usb/nvidia,tegra234-xusb.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: NVIDIA Tegra234 xHCI controller maintainers: - Thierry Reding <thierry.reding@gmail.com> - Jon Hunter <jonathanh@nvidia.com> description: | The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed by the Tegra XUSB pad controller. The xHCI controller controls up to eight ports; there are four USB 2.0 ports and four USB 3.2 Gen1 x1 ports. properties: compatible: const: nvidia,tegra234-xusb reg: items: - description: xHCI host registers - description: XUSB FPCI registers - description: XUSB bar2 registers reg-names: items: - const: hcd - const: fpci - const: bar2 interrupts: items: - description: xHCI host interrupt - description: mailbox interrupt clocks: items: - description: XUSB host clock - description: XUSB Falcon source clock - description: XUSB SuperSpeed clock - description: XUSB SuperSpeed source clock - description: XUSB HighSpeed clock source - description: XUSB FullSpeed clock source - description: USB PLL - description: reference clock - description: I/O PLL clock-names: items: - const: xusb_host - const: xusb_falcon_src - const: xusb_ss - const: xusb_ss_src - const: xusb_hs_src - const: xusb_fs_src - const: pll_u_480m - const: clk_m - const: pll_e interconnects: items: - description: read client - description: write client interconnect-names: items: - const: dma-mem # read - const: write iommus: maxItems: 1 nvidia,xusb-padctl: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the XUSB pad controller that is used to configure the USB pads used by the XHCI controller phys: minItems: 1 maxItems: 8 phy-names: minItems: 1 maxItems: 8 items: enum: - usb2-0 - usb2-1 - usb2-2 - usb2-3 - usb3-0 - usb3-1 - usb3-2 - usb3-3 power-domains: items: - description: XUSBC power domain (for Host and USB 2.0) - description: XUSBA power domain (for SuperSpeed) power-domain-names: items: - const: xusb_host - const: xusb_ss dma-coherent: true allOf: - $ref: usb-xhci.yaml unevaluatedProperties: false examples: - | #include <dt-bindings/clock/tegra234-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/memory/tegra234-mc.h> #include <dt-bindings/power/tegra234-powergate.h> usb@3610000 { compatible = "nvidia,tegra234-xusb"; reg = <0x03610000 0x40000>, <0x03600000 0x10000>, <0x03650000 0x10000>; reg-names = "hcd", "fpci", "bar2"; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, <&bpmp TEGRA234_CLK_XUSB_FALCON>, <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, <&bpmp TEGRA234_CLK_XUSB_SS>, <&bpmp TEGRA234_CLK_CLK_M>, <&bpmp TEGRA234_CLK_XUSB_FS>, <&bpmp TEGRA234_CLK_UTMIP_PLL>, <&bpmp TEGRA234_CLK_CLK_M>, <&bpmp TEGRA234_CLK_PLLE>; clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; interconnect-names = "dma-mem", "write"; iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; power-domain-names = "xusb_host", "xusb_ss"; nvidia,xusb-padctl = <&xusb_padctl>; phys = <&pad_lanes_usb2_0>; phy-names = "usb2-0"; }; |