Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 | # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys Designware Mobile Storage Host Controller maintainers: - Ulf Hansson <ulf.hansson@linaro.org> # Everything else is described in the common file properties: compatible: enum: - altr,socfpga-dw-mshc - img,pistachio-dw-mshc - snps,dw-mshc reg: maxItems: 1 interrupts: maxItems: 1 clocks: minItems: 2 maxItems: 2 description: Handle to "biu" and "ciu" clocks for the bus interface unit clock and the card interface unit clock. clock-names: items: - const: biu - const: ciu iommus: maxItems: 1 altr,sysmgr-syscon: $ref: /schemas/types.yaml#/definitions/phandle-array items: - items: - description: phandle to the sysmgr node - description: register offset that controls the SDMMC clock phase - description: register shift for the smplsel(drive in) setting description: This property is optional. Contains the phandle to System Manager block that contains the SDMMC clock-phase control register. The first value is the pointer to the sysmgr, the 2nd value is the register offset for the SDMMC clock phase register, and the 3rd value is the bit shift for the smplsel(drive in) setting. allOf: - $ref: synopsys-dw-mshc-common.yaml# - if: properties: compatible: contains: const: altr,socfpga-dw-mshc then: properties: altr,sysmgr-syscon: true else: properties: iommus: false altr,sysmgr-syscon: false required: - compatible - reg - interrupts - clocks - clock-names unevaluatedProperties: false examples: - | mmc@12200000 { compatible = "snps,dw-mshc"; reg = <0x12200000 0x1000>; interrupts = <0 75 0>; clocks = <&clock 351>, <&clock 132>; clock-names = "biu", "ciu"; dmas = <&pdma 12>; dma-names = "rx-tx"; resets = <&rst 20>; reset-names = "reset"; vmmc-supply = <&buck8>; #address-cells = <1>; #size-cells = <0>; broken-cd; bus-width = <8>; cap-mmc-highspeed; cap-sd-highspeed; card-detect-delay = <200>; max-frequency = <200000000>; clock-frequency = <400000000>; data-addr = <0x200>; fifo-depth = <0x80>; fifo-watermark-aligned; }; |