Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Microchip Sparx5 Mobile Storage Host Controller allOf: - $ref: mmc-controller.yaml maintainers: - Lars Povlsen <lars.povlsen@microchip.com> # Everything else is described in the common file properties: compatible: const: microchip,dw-sparx5-sdhci reg: maxItems: 1 interrupts: maxItems: 1 clocks: maxItems: 1 description: Handle to "core" clock for the sdhci controller. clock-names: items: - const: core microchip,clock-delay: description: Delay clock to card to meet setup time requirements. Each step increase by 1.25ns. $ref: /schemas/types.yaml#/definitions/uint32 minimum: 1 maximum: 15 required: - compatible - reg - interrupts - clocks - clock-names unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/microchip,sparx5.h> sdhci0: mmc@600800000 { compatible = "microchip,dw-sparx5-sdhci"; reg = <0x00800000 0x1000>; pinctrl-0 = <&emmc_pins>; pinctrl-names = "default"; clocks = <&clks CLK_ID_AUX1>; clock-names = "core"; assigned-clocks = <&clks CLK_ID_AUX1>; assigned-clock-rates = <800000000>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; bus-width = <8>; microchip,clock-delay = <10>; }; |