Based on kernel version 6.19. Page generated on 2026-02-12 08:38 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 | # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- $id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Rockchip designware mobile storage host controller description: Rockchip uses the Synopsys designware mobile storage host controller to interface a SoC with storage medium such as eMMC or SD/MMC cards. This file documents the combined properties for the core Synopsys dw mshc controller that are not already included in the synopsys-dw-mshc-common.yaml file and the Rockchip specific extensions. allOf: - $ref: synopsys-dw-mshc-common.yaml# maintainers: - Heiko Stuebner <heiko@sntech.de> # Everything else is described in the common file properties: compatible: oneOf: # for Rockchip RK2928 and before RK3288 - const: rockchip,rk2928-dw-mshc # for Rockchip RK3288 - const: rockchip,rk3288-dw-mshc - items: - enum: - rockchip,px30-dw-mshc - rockchip,rk1808-dw-mshc - rockchip,rk3036-dw-mshc - rockchip,rk3128-dw-mshc - rockchip,rk3228-dw-mshc - rockchip,rk3308-dw-mshc - rockchip,rk3328-dw-mshc - rockchip,rk3368-dw-mshc - rockchip,rk3399-dw-mshc - rockchip,rk3506-dw-mshc - rockchip,rk3528-dw-mshc - rockchip,rk3562-dw-mshc - rockchip,rk3568-dw-mshc - rockchip,rk3588-dw-mshc - rockchip,rv1108-dw-mshc - rockchip,rv1126-dw-mshc - const: rockchip,rk3288-dw-mshc # for Rockchip RK3576 with phase tuning inside the controller - const: rockchip,rk3576-dw-mshc reg: maxItems: 1 interrupts: maxItems: 1 clocks: minItems: 2 maxItems: 4 description: Handle to "biu" and "ciu" clocks for the bus interface unit clock and the card interface unit clock. If "ciu-drive" and "ciu-sample" are specified in clock-names, it should also contain handles to these clocks. clock-names: minItems: 2 items: - const: biu - const: ciu - const: ciu-drive - const: ciu-sample description: Apart from the clock-names "biu" and "ciu" two more clocks "ciu-drive" and "ciu-sample" are supported. They are used to control the clock phases, "ciu-sample" is required for tuning high speed modes. power-domains: maxItems: 1 rockchip,default-sample-phase: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 360 default: 0 description: The default phase to set "ciu-sample" at probing, low speeds or in case where all phases work at tuning time. If not specified 0 deg will be used. rockchip,desired-num-phases: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 360 default: 360 description: The desired number of times that the host execute tuning when needed. If not specified, the host will do tuning for 360 times, namely tuning for each degree. required: - compatible - reg - interrupts - clocks - clock-names unevaluatedProperties: false examples: - | #include <dt-bindings/clock/rk3288-cru.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> sdmmc: mmc@ff0c0000 { compatible = "rockchip,rk3288-dw-mshc"; reg = <0xff0c0000 0x4000>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; resets = <&cru SRST_MMC0>; reset-names = "reset"; fifo-depth = <0x100>; max-frequency = <150000000>; }; ... |