Based on kernel version 7.2. Page generated on 2026-08-20 08:41 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/reset/renesas,rzv2h-usb2phy-reset.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Renesas RZ/V2H(P) USB2PHY Port reset Control maintainers: - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> description: The RZ/V2H(P) USB2PHY Control mainly controls Port reset and power down of the USB2.0 PHY. properties: compatible: oneOf: - items: - enum: - renesas,r9a09g047-usb2phy-reset # RZ/G3E - renesas,r9a09g056-usb2phy-reset # RZ/V2N - const: renesas,r9a09g057-usb2phy-reset - const: renesas,r9a09g057-usb2phy-reset # RZ/V2H(P) reg: maxItems: 1 clocks: maxItems: 1 resets: maxItems: 1 power-domains: maxItems: 1 '#reset-cells': const: 0 '#mux-state-cells': const: 1 required: - compatible - reg - clocks - resets - power-domains - '#reset-cells' - '#mux-state-cells' additionalProperties: false examples: - | #include <dt-bindings/clock/renesas,r9a09g057-cpg.h> reset-controller@15830000 { compatible = "renesas,r9a09g057-usb2phy-reset"; reg = <0x15830000 0x10000>; clocks = <&cpg CPG_MOD 0xb6>; resets = <&cpg 0xaf>; power-domains = <&cpg>; #reset-cells = <0>; #mux-state-cells = <1>; }; |