Based on kernel version 6.11
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/reset/nuvoton,npcm750-reset.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Nuvoton NPCM Reset controller maintainers: - Tomer Maimon <tmaimon77@gmail.com> properties: compatible: enum: - nuvoton,npcm750-reset # Poleg NPCM7XX SoC - nuvoton,npcm845-reset # Arbel NPCM8XX SoC reg: maxItems: 1 '#reset-cells': const: 2 nuvoton,sysgcr: $ref: /schemas/types.yaml#/definitions/phandle description: a phandle to access GCR registers. nuvoton,sw-reset-number: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 1 maximum: 4 description: | Contains the software reset number to restart the SoC. If not specified, software reset is disabled. required: - compatible - reg - '#reset-cells' - nuvoton,sysgcr additionalProperties: false examples: - | #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h> rstc: rstc@f0801000 { compatible = "nuvoton,npcm750-reset"; reg = <0xf0801000 0x70>; #reset-cells = <2>; nuvoton,sysgcr = <&gcr>; nuvoton,sw-reset-number = <2>; }; // Specifying reset lines connected to IP NPCM7XX modules spi0: spi { resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>; }; |