Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 | # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- $id: http://devicetree.org/schemas/reset/allwinner,sun6i-a31-clock-reset.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Allwinner A31 Peripheral Reset Controller maintainers: - Chen-Yu Tsai <wens@csie.org> - Maxime Ripard <mripard@kernel.org> deprecated: true select: properties: compatible: contains: enum: - allwinner,sun6i-a31-ahb1-reset - allwinner,sun6i-a31-clock-reset # The PRCM on the A31 and A23 will have the reg property missing, # since it's set at the upper level node, and will be validated by # PRCM's schema. Make sure we only validate standalone nodes. required: - compatible - reg properties: "#reset-cells": const: 1 description: > This additional argument passed to that reset controller is the offset of the bit controlling this particular reset line in the register. compatible: enum: - allwinner,sun6i-a31-ahb1-reset - allwinner,sun6i-a31-clock-reset reg: maxItems: 1 required: - "#reset-cells" - compatible - reg additionalProperties: false examples: - | ahb1_rst: reset@1c202c0 { #reset-cells = <1>; compatible = "allwinner,sun6i-a31-ahb1-reset"; reg = <0x01c202c0 0xc>; }; - | apbs_rst: reset@80014b0 { #reset-cells = <1>; compatible = "allwinner,sun6i-a31-clock-reset"; reg = <0x080014b0 0x4>; }; ... |