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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Marvell NAND Flash Controller (NFC) maintainers: - Miquel Raynal <miquel.raynal@bootlin.com> properties: compatible: oneOf: - items: - const: marvell,armada-8k-nand-controller - const: marvell,armada370-nand-controller - enum: - marvell,ac5-nand-controller - marvell,armada370-nand-controller - marvell,pxa3xx-nand-controller - description: legacy bindings deprecated: true enum: - marvell,armada-8k-nand - marvell,armada370-nand - marvell,pxa3xx-nand reg: maxItems: 1 interrupts: maxItems: 1 clocks: description: Shall reference the NAND controller clocks, the second one is is only needed for the Armada 7K/8K SoCs minItems: 1 maxItems: 2 clock-names: minItems: 1 items: - const: core - const: reg dmas: maxItems: 1 dma-names: items: - const: data marvell,system-controller: $ref: /schemas/types.yaml#/definitions/phandle description: Syscon node that handles NAND controller related registers patternProperties: "^nand@[a-f0-9]$": type: object $ref: raw-nand-chip.yaml properties: reg: minimum: 0 maximum: 3 nand-rb: items: - minimum: 0 maximum: 1 nand-ecc-step-size: const: 512 nand-ecc-strength: enum: [1, 4, 8, 12, 16] nand-ecc-mode: const: hw marvell,nand-keep-config: $ref: /schemas/types.yaml#/definitions/flag description: Orders the driver not to take the timings from the core and leaving them completely untouched. Bootloader timings will then be used. marvell,nand-enable-arbiter: $ref: /schemas/types.yaml#/definitions/flag description: To enable the arbiter, all boards blindly used it, this bit was set by the bootloader for many boards and even if it is marked reserved in several datasheets, it might be needed to set it (otherwise it is harmless). deprecated: true required: - reg - nand-rb unevaluatedProperties: false required: - compatible - reg - interrupts - clocks allOf: - $ref: nand-controller.yaml# - if: properties: compatible: contains: const: marvell,pxa3xx-nand-controller then: required: - dmas - dma-names - if: properties: compatible: contains: const: marvell,armada-8k-nand-controller then: properties: clocks: minItems: 2 clock-names: minItems: 2 required: - marvell,system-controller else: properties: clocks: minItems: 1 clock-names: minItems: 1 unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> nand_controller: nand-controller@d0000 { compatible = "marvell,armada370-nand-controller"; reg = <0xd0000 0x54>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; clocks = <&coredivclk 0>; nand@0 { reg = <0>; label = "main-storage"; nand-rb = <0>; nand-ecc-mode = "hw"; marvell,nand-keep-config; nand-on-flash-bbt; nand-ecc-strength = <4>; nand-ecc-step-size = <512>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "Rootfs"; reg = <0x00000000 0x40000000>; }; }; }; }; - | cp0_nand_controller: nand-controller@720000 { compatible = "marvell,armada-8k-nand-controller", "marvell,armada370-nand-controller"; reg = <0x720000 0x54>; #address-cells = <1>; #size-cells = <0>; interrupts = <115 IRQ_TYPE_LEVEL_HIGH>; clock-names = "core", "reg"; clocks = <&cp0_clk 1 2>, <&cp0_clk 1 17>; marvell,system-controller = <&cp0_syscon0>; nand@0 { reg = <0>; label = "main-storage"; nand-rb = <0>; nand-ecc-mode = "hw"; nand-ecc-strength = <8>; nand-ecc-step-size = <512>; }; }; - | nand-controller@43100000 { compatible = "marvell,pxa3xx-nand-controller"; reg = <0x43100000 90>; interrupts = <45>; clocks = <&clks 1>; clock-names = "core"; dmas = <&pdma 97 3>; dma-names = "data"; #address-cells = <1>; #size-cells = <0>; nand@0 { reg = <0>; nand-rb = <0>; nand-ecc-mode = "hw"; marvell,nand-keep-config; }; }; ... |